SBOSA75B July   2021  – November 2021 INA823

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Gain-Setting Function
        1. 8.3.1.1 Gain Drift
      2. 8.3.2 Input Common-Mode Voltage Range
      3. 8.3.3 Input Protection
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Bias Current Return Path
    2. 9.2 Typical Applications
      1. 9.2.1 Resistive-Bridge Pressure Sensor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Supporting High Common-Mode Voltage in PLC Input Modules
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 PSpice® for TI
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Design Procedure

The gain of the IA is calculated so that the circuit operates at unity gain, where VOUT = VDIFF.

The single-ended input impedance, Rin(SE), of the circuit is the sum of the scaling resistors (Rf + Ri). To minimize the error that is caused by the tolerance of the scaling resistors, keep Rin > 1 MΩ.

Ideally, choose the resistors so that Rf / Ri = Rf' / Ri'. In the real world, designers have to trade off between the mismatch of ratios that degrades the common-mode rejection ratio (CMRR) and the acceptable cost for the design.

The following text describe how to estimate the CMRR performance of the external resistor scaling approach. In the calculation of CMRR, the following factors are considered:

  • Take into account the number of resistors, which is estimated by √n, where n is the number of resistors applied. In this case, this estimation results in a factor of 2.
  • ΔR / R is the resistor matching ratio. The resistor tolerance for all four resistors is 0.1%.
  • Take into account that a normal production distribution of the resistor value with a standard deviation of ±3 σ (99.7%). In this case, the assumption results in a factor σ = 1/3 = 0.33 into the equation.

Equation 9 calculates the common-mode rejection ratio with given factors:

Equation 9. C M R R d B   =   G 1   + 1 α Δ R R n
Equation 10. CMRR dB  =  0.25 +1 0.33∙0.1%∙√4   =   6 5.5 dB

The scaling ratio G1 is calculated by:

Equation 11. G 1   =   R f   R f +   R i

where

  • Rf is variable
  • Ri is fixed at 750 kΩ.

Figure 9-6 shows a comparison between the CMRR performance at worst-case (α neglected) and considering normal distribution for different gain settings of G1.

For more details about the calculation of CMRR, see the Difference amplifier (subtractor) circuit analog engineer's circuit.