SBOSA75B July   2021  – November 2021 INA823

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Gain-Setting Function
        1. 8.3.1.1 Gain Drift
      2. 8.3.2 Input Common-Mode Voltage Range
      3. 8.3.3 Input Protection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Bias Current Return Path
    2. 9.2 Typical Applications
      1. 9.2.1 Resistive-Bridge Pressure Sensor
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Supporting High Common-Mode Voltage in PLC Input Modules
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 PSpice® for TI
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Typical Characteristics

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, CL = 0 pF, VCM = VREF = 0 V, and G = 1 (unless otherwise noted)

Table 7-1 Table of Graphs
FIGURE TITLEFIGURE NUMBER
Typical Distribution Graphs
Typical Distribution of Input Stage Offset VoltageFigure 7-1
Typical Distribution of Input Stage Offset Voltage DriftFigure 7-2
Typical Distribution of Output Stage Offset VoltageFigure 7-3
Typical Distribution of Output Stage Offset Voltage DriftFigure 7-4
Typical Distribution of Inverting Input Bias CurrentFigure 7-5
Typical Distribution of Noninverting Input Bias CurrentFigure 7-6
Typical Distribution of Input Offset CurrentFigure 7-7
Typical CMRR Distribution, G = 1Figure 7-8
Typical CMRR Distribution, G = 10Figure 7-9
Typical Gain Error DistributionFigure 7-10
vs Temperature Graphs
Input Stage Offset Voltage vs TemperatureFigure 7-11
Output Stage Offset Voltage vs TemperatureFigure 7-12
Input Bias Current vs TemperatureFigure 7-13
Input Offset Current vs TemperatureFigure 7-14
CMRR vs Temperature, G = 1Figure 7-15
CMRR vs Temperature, G = 10Figure 7-16
Gain Error vs Temperature, G = 1Figure 7-17
Gain Error vs Temperature, G = 100Figure 7-18
Supply Current vs TemperatureFigure 7-19
AC Performance Graphs
Closed-Loop Gain vs FrequencyFigure 7-20
CMRR vs Frequency (RTI)Figure 7-21
CMRR vs Frequency (RTI, 1-kΩ source imbalance)Figure 7-22
Positive PSRR vs Frequency (RTI)Figure 7-23
Negative PSRR vs Frequency (RTI)Figure 7-24
Voltage Noise Spectral Density vs Frequency (RTI)Figure 7-25
Current Noise Spectral Density vs Frequency (RTI)Figure 7-26
0.1-Hz to 10-Hz RTI Voltage NoiseFigure 7-27
0.1-Hz to 10-Hz RTI Voltage Noise, G = 1000Figure 7-28
Small-Signal Response, G = 1Figure 7-29
Small-Signal Response, G = 10Figure 7-30
Small-Signal Response, G = 100Figure 7-31
Small-Signal Response, G = 1000Figure 7-32
Overshoot vs Capacitive LoadsFigure 7-33
Large-Signal Step ResponseFigure 7-34
Settling Time vs Step SizeFigure 7-35
Large-Signal Frequency ResponseFigure 7-36
Closed-Loop Output Impedance vs FrequencyFigure 7-37
Input and Output Voltage Graphs
Input Current vs Input OvervoltageFigure 7-38
Gain Nonlinearity, G = 1Figure 7-39
Gain Nonlinearity, G = 10Figure 7-40
Gain Nonlinearity, G = 100Figure 7-41
Gain Nonlinearity, G = 1000Figure 7-42
Positive Input Bias Current vs Common‑Mode Voltage (VS–)Figure 7-43
Positive Input Bias Current vs Common‑Mode Voltage (VS+)Figure 7-44
Negative Input Bias Current vs Common‑Mode Voltage (VS–)Figure 7-45
Negative Input Bias Current vs Common‑Mode Voltage (VS+)Figure 7-46
Offset Voltage vs Common-Mode Voltage, VS = 30 VFigure 7-47
Offset Voltage vs Common-Mode Voltage, VS = 2.7 VFigure 7-48
Positive Output Voltage Swing vs Output Current, VS = 30 VFigure 7-49
Negative Output Voltage Swing vs Output Current, VS = 30 VFigure 7-50
Positive Output Voltage Swing vs Output Current, VS = 2.7 VFigure 7-51
Negative Output Voltage Swing vs Output Current, VS = 2.7 VFigure 7-52
Input Common-Mode Voltage vs Output Voltage, VS = 2.7 V, G = 1Figure 7-53
Input Common-Mode Voltage vs Output Voltage, VS = 2.7 V, G = 1Figure 7-54
Input Common-Mode Voltage vs Output Voltage, VS = 5 V, G = 1Figure 7-55
Input Common-Mode Voltage vs Output Voltage, VS = 5 V, G = 100Figure 7-56
Input Common-Mode Voltage vs Output Voltage, VS = 24 V and VS = 30 V, G = 1Figure 7-57
Input Common-Mode Voltage vs Output Voltage, VS = 24 V and VS = 30 V, G = 10Figure 7-58
GUID-20210610-CA0I-VQHX-QJQM-MWD79S211RTL-low.png
N = 1225Mean = 3.63 μVStd Dev = 18.0 μV
Figure 7-1 Typical Distribution of Input Stage Offset Voltage
GUID-20210610-CA0I-N7ZS-C68M-JRZTXN0R64RN-low.png
N = 1225Mean = 48.0 μVStd Dev = 92.4 μV
Figure 7-3 Typical Distribution of Output Stage Offset Voltage
N = 1200Mean = 1.21 nAStd Dev = 0.384 nA
Figure 7-5 Typical Distribution of Inverting Input Bias Current
N = 1170Mean = –0.092 nAStd Dev = 0.35 nA
Figure 7-7 Typical Distribution of Input Offset Current
GUID-20210610-CA0I-SLVM-XMDS-DV8D5PDBGB3P-low.png
N = 1225Mean = –0.0599 μV/VStd. Dev = 0.710 μV/V
G = 10
Figure 7-9 Typical CMRR Distribution
 
Figure 7-11 Input Stage Offset Voltage vs Temperature
 
Figure 7-13 Input Bias Current vs Temperature
G = 1
Figure 7-15 CMRR vs Temperature
G = 1Average of 120 unitsNormalized at +25°C
Figure 7-17 Gain Error vs Temperature
 
Figure 7-19 Supply Current vs Temperature
 
Figure 7-21 CMRR vs Frequency (RTI)
 
Figure 7-23 Positive PSRR vs Frequency (RTI)
 
Figure 7-25 Voltage Noise Spectral Density vs Frequency (RTI)
GUID-20210610-CA0I-SJ9Z-CSDL-5WF2WXTSMNQS-low.png
 
Figure 7-27 0.1-Hz to 10-Hz RTI Voltage Noise
G = 1RL = 10 kΩCL = 100 pF
Figure 7-29 Small-Signal Response
G = 100RL = 10 kΩCL = 100 pF
Figure 7-31 Small-Signal Response
 
Figure 7-33 Overshoot vs Capacitive Loads
 
Figure 7-35 Settling Time vs Step Size
 
Figure 7-37 Closed-Loop Output Impedance vs Frequency
 
Figure 7-39 Gain Nonlinearity
 
Figure 7-41 Gain Nonlinearity
 
Figure 7-43 Positive Input Bias Current vs Common‑Mode Voltage (VS–)
 
Figure 7-45 Negative Input Bias Current vs Common‑Mode Voltage (VS–)
VS = ±15 V
Figure 7-47 Offset Voltage vs Common-Mode Voltage
VS = ±15 V
Figure 7-49 Positive Output Voltage Swing vs Output Current
VS = ±1.35 V
Figure 7-51 Positive Output Voltage Swing vs Output Current
GUID-20210616-CA0I-GZQF-WG3Q-FGGMZRCKJ5HB-low.png
VS = 2.7 VG = 1
Figure 7-53 Input Common-Mode Voltage vs Output Voltage
GUID-20210616-CA0I-2ZVR-SJJM-XZHTQ0L7MCVN-low.png
VS = 5 VG = 1
Figure 7-55 Input Common-Mode Voltage vs Output Voltage
GUID-20210616-CA0I-RPWH-NGR8-J3XM3CRMQM0J-low.png
G = 1
Figure 7-57 Input Common-Mode Voltage vs Output Voltage
GUID-20210624-CA0I-ZPSS-B1XG-MGGWBZC63MBF-low.png
N = 30Mean = –0.024 μV/ºCStd Dev = 0.177 μV//ºC
Figure 7-2 Typical Distribution of Input Stage Offset Voltage Drift
GUID-20210624-CA0I-Z9XT-MTX1-N5C6VNRLKLRJ-low.png
N = 30Mean = 0.17 μV/ºCStd Dev = 0.795 μV/ºC
Figure 7-4 Typical Distribution of Output Stage Offset Voltage Drift
N = 1200Mean = 1.11 nAStd Dev = 0.368 nA
Figure 7-6 Typical Distribution of Noninverting Input Bias Current
N = 1225Mean = –0.22 μV/VStd Dev = 6.95 μV/V
Figure 7-8 Typical CMRR Distribution
N = 550Mean = –0.0334 %Std. Dev = 0.0433 %
G = 10
Figure 7-10 Typical Gain Error Distribution
 
Figure 7-12 Output Stage Offset Voltage vs Temperature
 
Figure 7-14 Input Offset Current vs Temperature
G = 10
Figure 7-16 CMRR vs Temperature
G = 100Average of 120 unitsNormalized at +25°C
Figure 7-18 Gain Error vs Temperature
 
Figure 7-20 Closed-Loop Gain vs Frequency
 
Figure 7-22 CMRR vs Frequency (RTI, 1-kΩ source imbalance)
 
Figure 7-24 Negative PSRR vs Frequency (RTI)
 
Figure 7-26 Current Noise Spectral Density vs Frequency (RTI)
GUID-20210610-CA0I-H2ZJ-J15G-TWBJ3XZBN9ND-low.png
 
Figure 7-28 0.1-Hz to 10-Hz RTI Voltage Noise
G = 10RL = 10 kΩCL = 100 pF
Figure 7-30 Small-Signal Response
G = 1000RL = 10 kΩCL = 100 pF
Figure 7-32 Small-Signal Response
 
Figure 7-34 Large-Signal Step Response
 
Figure 7-36 Large-Signal Frequency Response
VS = ±15 V
Figure 7-38 Input Current vs Input Overvoltage
 
Figure 7-40 Gain Nonlinearity
 
Figure 7-42 Gain Nonlinearity
 
Figure 7-44 Positive Input Bias Current vs Common‑Mode Voltage (VS+)
 
Figure 7-46 Negative Input Bias Current vs Common‑Mode Voltage (VS+)
VS = ±1.35 V
Figure 7-48 Offset Voltage vs Common-Mode Voltage
VS = ±15 V
Figure 7-50 Negative Output Voltage Swing vs Output Current
VS = ±1.35 V
Figure 7-52 Negative Output Voltage Swing vs Output Current
GUID-20210616-CA0I-VSQR-FRCH-DXXT1ZZWQ7SQ-low.png
VS = 2.7 VG = 100
Figure 7-54 Input Common-Mode Voltage vs Output Voltage
GUID-20210616-CA0I-MGHF-T38Z-VCTFH8HXW7GS-low.png
VS = 5 VG = 100
Figure 7-56 Input Common-Mode Voltage vs Output Voltage
GUID-20210616-CA0I-NGPZ-G3XF-VZN7PFXCTB5M-low.png
G > 10
Figure 7-58 Input Common-Mode Voltage vs Output Voltage