Attention to good layout practices is
always recommended. For best operational performance of the device, use the
following PCB layout practices:
- Make sure that both input
paths are well-matched for source impedance and capacitance to avoid
converting common-mode signals into differential signals.
- Use bypass capacitors to
reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
- Connect low-ESR,
0.1-µF ceramic bypass capacitors between each supply pin and ground,
placed as close to the device as possible. A single bypass capacitor
from V+ to ground is applicable for single-supply applications.
- Route the input traces as far
away from the supply or output traces as possible to reduce parasitic
coupling. If these traces cannot be kept separate, crossing the sensitive
trace perpendicular is much better than crossing in parallel with the noisy
- Place the external components
as close to the device as possible.
- Use short, symmetric, and
wide traces to connect the external gain resistor to minimize capacitance
mismatch between the RG pins.
- Keep the traces as short as