SLLSFO4C December   2022  – September 2023 ISOM8710 , ISOM8711

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics—DC 
    10. 7.10 Switching Characteristics, ISOM8710
    11. 7.11 Switching Characteristics, ISOM8711
    12. 7.12 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Sizing RIN
        2. 10.2.2.2 Driving the Input with a Buffer
        3. 10.2.2.3 Calculating RL for ISOM8711
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • DFF|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.2.2.3 Calculating RL for ISOM8711

An RL component is not necessary if using ISOM8710. Since ISOM8711 features an open-collector OUT pin, a pull-up resistor, RL, connecting OUT to VCC is necessary for transmission of logic-HIGH signals. This pull-up resistor pulls the line HIGH when the line is not driven LOW by the open-collector OUT pin. The value of RL is an important design consideration for systems using ISOM8711 since a value that is too low (strong pull-up) can result in excessive power dissipation while a value that is too high (weak pull-up) can lead to signal loss at high frequencies. Below are equations for the pullup resistor calculation.

Step 1: Calculate the Minimum RL

An RL value that is too small can prevent the OUT pin of the ISOM8711 from being able to drive LOW signals. Thus, the equation for minimum RL is a function of VCC, the maximum voltage level that can be read as a LOW signal by the input buffers of the connected device, VIL, and the maximum current OUT can sink in LOW signal states, IOS, as shown in Equation 5.

Equation 5. RL MIN = VCC - VIL MAXIOS MAX

Most CMOS-input devices have maximum VIL thresholds as a function of the supply, like 30% the VCC level, while TTL-input devices can have a fixed VIL threshold regardless of the supply, like 0.8 V.

For an example VCC = 3.3 V, a maximum VIL of 0.99 V, and maximum IOS of 13 mA, minimum RL is calculated as:

Equation 6. RL MIN = 3.3 V - 0.99 V13 mA =178 Ω

Step 2: Calculate the Maximum RL

The maximum pullup resistance is limited by the load and trace capacitance, CL, of the OUT signal line due to standard rise time specifications. If the pullup resistor value is too high, the signal line cannot rise to a logical HIGH before being pulled LOW again. Thus, to calculate the maximum appropriate RL value, the maximum allowable rise time, tR, must first be calculated using Equation 7 and the maximum allowable rise time as a percentage of the data rate period and the maximum data rate of the signal to be transmitted.

Equation 7. tR =2 × rise time %data rateMAX

This rise time can be set equal to the time constant factor needed for a 10% to 90% transition to occur and solved for the resistor value, as shown in Equation 8:

Equation 8. RL MAX = tR2.2 × CL

For example, if rise time can occupy 15% of the period for a 10-Mbps signal, rise time in seconds is calculated as:

Equation 9. tR =2 × 15 %10 Mbps =30 ns

With a 30-ns rise-time and a typical load capacitance of 2 pF, maximum RL is estimated as:

Equation 10. RL MAX = 30 ns2.2 × 2 pF =6.82 kΩ

Step 3: Select RL to be Between RL (min) and RL (max)

The selected RL value should be between the calculated RL [min] and RL [max] values to meet the design criteria. A lower value will enable faster signal transmission or higher load and trace capacitances while a higher value will consume lower power.