SLLSFC6B November   2021  – July 2022 ISOUSB111


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Test Circuits
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply Options
      2. 8.3.2 Power Up
      3. 8.3.3 Symmetric Operation, Dual-Role Port and Role-Reversal
      4. 8.3.4 Connect and Speed Detection
      5. 8.3.5 Disconnect Detection
      6. 8.3.6 Reset
      7. 8.3.7 LS/FS Message Traffic
      8. 8.3.8 L2 Power Management State (Suspend) and Resume
      9. 8.3.9 L1 Power Management State (Sleep) and Resume
    4. 8.4 Device Functional Modes
  9. Power Supply Recommendations
  10. 10Application and Implementation
    1. 10.1 Typical Application
      1. 10.1.1 Isolated Host or Hub
      2. 10.1.2 Isolated Peripheral - Self-Powered
      3. 10.1.3 Isolated Peripheral - Bus-Powered
      4. 10.1.4 Application Curve
        1. Insulation Lifetime
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Layout Example
      2. 11.1.2 PCB Material
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

Two layers are sufficient to accomplish a low EMI PCB design.

  • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link.
  • For best performance, it is recommended to minimize the length of D+/D- board traces from the MCU to ISOUSB111, and from ISOUSB111 to the connector. Vias and stubs on D+/D- lines must be avoided.
  • Placing a solid ground plane just below the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. D+ and D- traces must be designed for 90-Ω differential impedance and as close to 45-Ω single ended impedance as possible.
  • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in2.
  • Decoupling capacitors must be placed on the top layer, and the routing between the capacitors and the corresponding to supply and ground pins must be completed in the top layer itself. There should not be any vias in the routing path between the decoupling capacitors and the corresponding supply and ground pins.
  • ESD structures must be placed on the top layer, close to the connector, and right on the D+/D- traces without vias. Ground routing for the ESD structures must be made in the top layer if possible, else must have a strong connection to the ground plane with multiple vias.
  • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.