Optimum LDC1312/LDC1314 performance requires a clean reference clock with a limited frequency range. The device provides digital dividers for the ƒCLK and the sensor inputs. The dividers provide flexibility in system design, so that the full range of sensor frequencies can be supported with available fCLK. Each channel has a dedicated divider configuration. Higher reference frequencies provide a higher sample rate for a given resolution.
Figure 54 shows the clock dividers and multiplexers of the LDC.
(1) LDC1314 only
In Figure 54, the key clocks are ƒINx, ƒREFx, and ƒCLK. ƒCLK is selected from either the internal clock source or external clock source (CLKIN). The frequency measurement reference clock, ƒREF, is derived from the ƒCLK source.
The internal oscillator is highly stable across temperature and is suitable for most LDC1312/4 applications. Applications requiring matched performance across multiple LDC1312/4 devices and/or requiring higher long-term stability may need an external oscillator. Note that some internal functions, such as watchdog timers, always use ƒINT for timing.
The ƒINx clock is derived from sensor frequency for channel x, ƒSENSORx. ƒREFx and ƒINx must meet the requirements listed in Table 40, depending on whether ƒCLK (reference clock) is the internal or external clock.
|MODE(1)||REFERENCE SOURCE||VALID ƒREFx RANGE||VALID ƒINx RANGE||SET FIN_DIVIDERx to||VALID SETTLECOUNTx SETTINGS||VALID RCOUNTx SETTINGS|
|Multi-Channel||Internal||ƒREFx≤ 55 MHz||< ƒREFx /4||≥ b0001 (2)||> 3||> 8|
|External||ƒREFx ≤ 40 MHz|
|Single-Channel||Either external or internal||ƒREFx ≤ 35 MHz|
Table 41 shows the clock configuration registers. Each input channel has a dedicated configuration which can be set independently.
|All||ƒCLK = Reference Clock Source||CONFIG, addr 0x1A||REF_CLK_SRC ||b0 = internal oscillator is used as the reference clock
b1 = external clock source is used as the reference clock
|0||ƒREF0||CLOCK_DIVIDERS0, addr 0x14||FREF_DIVIDER0 [9:0]||ƒREF0 = ƒCLK / FREF_DIVIDER0|
|1||ƒREF1||CLOCK_DIVIDERS1, addr 0x15||FREF_DIVIDER1 [9:0]||ƒREF1 = ƒCLK / FREF_DIVIDER1|
|2||ƒREF2||CLOCK_DIVIDERS2, addr 0x16||FREF_DIVIDER2 [9:0]||ƒREF2 = ƒCLK / FREF_DIVIDER2|
|3||ƒREF3||CLOCK_DIVIDERS3, addr 0x17||FREF_DIVIDER3 [9:0]||ƒREF3 = ƒCLK / FREF_DIVIDER3|
|0||ƒIN0||CLOCK_DIVIDERS0, addr 0x14||FIN_DIVIDER0 [15:12]||ƒIN0 = ƒSENSOR0 / FIN_DIVIDER0|
|1||ƒIN1||CLOCK_DIVIDERS1, addr 0x15||FIN_DIVIDER1 [15:12]||ƒIN1 = ƒSENSOR1 / FIN_DIVIDER1|
|2||ƒIN2||CLOCK_DIVIDERS2, addr 0x16||FIN_DIVIDER2 [15:12]||ƒIN2 = ƒSENSOR2 / FIN_DIVIDER2|
|3||ƒIN3||CLOCK_DIVIDERS3, addr 0x17||FIN_DIVIDER3 [15:12]||ƒIN3 = ƒSENSOR3 / FIN_DIVIDER3|