SNVS671F February   2011  – May 2019 LM21212-1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application Circuit
  4. Revision History
  5. Description
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Performance Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Frequency Synchronization
      2. 8.3.2 Precision Enable
      3. 8.3.3 UVLO
      4. 8.3.4 Current Limit
      5. 8.3.5 Short-Circuit Protection
      6. 8.3.6 Thermal Protection
      7. 8.3.7 Power-Good Flag
      8. 8.3.8 Light Load Operation
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Detailed Design Procedure
        1. 9.2.1.1 Custom Design With WEBENCH® Tools
        2. 9.2.1.2 Output Voltage
        3. 9.2.1.3 Precision Enable
        4. 9.2.1.4 Soft Start
        5. 9.2.1.5 Inductor Selection
        6. 9.2.1.6 Output Capacitor Selection
        7. 9.2.1.7 Input Capacitor Selection
        8. 9.2.1.8 Control Loop Compensation
      2. 9.2.2 Application Curves
  10. 10Layout
    1. 10.1 Pcb Layout Considerations
    2. 10.2 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With Webench® Tools
    2. 11.2 Receiving Notification Of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, And Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Performance Characteristics

Unless otherwise specified: VVIN = 5V, VOUT = 1.2V, L= 0.56µH (1.8mΩ RDCR), CSS = 33nF, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others.
LM21212-1 30119953.gif
Figure 1. Efficiency
LM21212-1 30119977.gif
VOUT = 2.5 V fSW= 300 KHz Inductor P/N Ser2010-102mld
Figure 3. Efficiency
LM21212-1 30119955.gif
Figure 5. Line Regulation
LM21212-1 30119975.gif
Figure 7. Non-Switching IAVIN and IPVIN vs Temperature
LM21212-1 30119971.gif
Figure 9. Enable Threshold and Hysteresis vs Temperature
LM21212-1 30119973.gif
Figure 11. Enable Low Current vs Temperature
LM21212-1 30119972.gif
Figure 13. Minimum On-Time vs Temperature
LM21212-1 30119958.gif
Figure 15. Peak Current Limit vs Temperature
LM21212-1 30119960.gif
4 µs/DIV
Figure 17. Sync Signal Acquired
LM21212-1 30119966.gif
200 µs/DIV
Figure 19. Start-up With SS/TRK Open Circuit
LM21212-1 30119980.gif
100 µs/DIV
Figure 21. Output Overcurrent Condition
LM21212-1 30119956.gif
Figure 2. Efficiency
LM21212-1 30119954.gif
Figure 4. Load Regulation
LM21212-1 30119957.gif
Figure 6. Non-Switching IQTOTAL vs VIN
LM21212-1 30119976.gif
Figure 8. VFB vs Temperature
LM21212-1 30119970.gif
Figure 10. UVLO Threshold and Hysteresis vs Temperature
LM21212-1 30119974.gif
Figure 12. OVP/UVP Threshold vs Temperature
LM21212-1 30119968.gif
Figure 14. FET Resistance vs Temperature
LM21212-1 30119965.gif
4 µs/DIV
Figure 16. Sync Signal Lost
LM21212-1 30119963.gif
2 ms/DIV
Figure 18. Start-up With Prebiased Output
LM21212-1 30119967.gif
200 ms/DIV
Figure 20. Start-up With Applied Track Signal