Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LM25117 is a step-down dc-dc controller. The device is typically used to convert a higher dc voltage to a lower dc voltage. Use the following design procedure to select component values. Alternately, use the WEBENCH® software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design.
Open loop response of the regulator is defined as the product of modulator transfer function and feedback transfer function. When plotted on a dB scale, the open loop gain is shown as the sum of modulator gain and feedback gain.
The modulator transfer function includes a power stage transfer function with an embedded current loop and can be simplified as one pole and one zero system as shown in the following equations.
If the ESR of COUT (RESR) is very small, the modulator transfer function can be further simplified to a one pole system and the voltage loop can be closed with only two loop compensation components, RCOMP and CCOMP, leaving a single pole response at the crossover frequency. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin.
The feedback transfer function includes the feedback resistor divider and loop compensation of the error amplifier. RCOMP, CCOMP and optional CHF configure the error amplifier gain and phase characteristics and create a pole at origin, a low frequency zero and a high frequency pole. This is shown mathematically in the following equations.
The pole at the origin minimizes output steady state error. The low frequency zero should be placed to cancel the load pole of the modulator. The high frequency pole can be used to cancel the zero created by the output capacitor ESR or to decrease noise susceptibility of the error amplifier. By placing the low frequency zero an order of magnitude less than the crossover frequency, the maximum amount of phase boost can be achieved at the crossover frequency. The high frequency pole should be placed well beyond the crossover frequency since the addition of CHF adds a pole in the feedback transfer function.
The crossover frequency (loop bandwidth) is usually selected between one twentieth and one fifth of the fSW. In a simplified formula, the crossover frequency can be defined as:
For higher crossover frequency, RCOMP can be increased, while proportionally decreasing CCOMP. Conversely, decreasing RCOMP while proportionally increasing CCOMP, results in lower bandwidth while keeping the same zero frequency in the feedback transfer function.
The sampled gain inductor pole is inversely proportional to the K factor, which is defined as:
The maximum achievable loop bandwidth, in fact, is limited by this sampled gain inductor pole. In traditional current mode control, the maximum achievable loop bandwidth varies with input voltage. With the LM25117’s unique slope compensation scheme, the sampled gain inductor pole is independent of changes to the input voltage. This frees the user from additional concerns in wide varying input range applications and is an advantage of the LM25117.
If the sampled gain inductor pole or the ESR zero is close to the crossover frequency, it is recommended that the comprehensive formulas in Table 1 be used and the stability should be checked by a network analyzer. The modulator transfer function can be measured and the feedback transfer function can be configured for the desired open loop transfer function. If a network analyzer is not available, step load transient tests can be performed to verify acceptable performance. The step load goal is minimum overshoot/undershoot with a damped response.
Peak current mode regulators can exhibit unstable behavior when operating above 50% duty cycle. This behavior is known as sub-harmonic oscillation and is characterized by alternating wide and narrow pulses at the SW pin. Sub-harmonic oscillation can be prevented by adding an additional voltage ramp (slope compensation) on top of the sensed inductor current shown in Figure 20. By choosing K≥1, the regulator will not be subject to sub-harmonic oscillation caused by a varying input voltage.
In time-domain analysis, the steady-state inductor current starts and ends at the same value during one clock cycle. If the magnitude of the end-of-cycle current error, dI1, caused by an initial perturbation, dI0, is less than the magnitude of dI0 or dI1/dI0 > -1, the perturbation naturally disappears after a few cycles. When dI1/dI0 < -1, the initial perturbation does not disappear, resulting in sub-harmonic oscillation in steady-state operation.
dI1/dI0 can be calculated by:
The relationship between dI1/dI0 and K factor is illustrated graphically in Figure 31.
The minimum value of K is 0.5. When K<0.5, the amplitude of dI1 is greater than the amplitude of dI0 and any initial perturbation results in sub-harmonic oscillation. If K=1, any initial perturbation will be removed in one switching cycle. This is known as one-cycle damping. When -1<dl1/dl0<0, any initial perturbation will be under-damped. Any perturbation will be over-damped when 0<dl1/dl0<1.
In the frequency-domain, Q, the quality factor of the sampling gain term in the modulator transfer function, is used to predict the tendency for sub-harmonic oscillation, which is defined as:
The relationship between Q and K factor is illustrated graphically in Figure 32.
The minimum value of K is 0.5 again. This is the same as time domain analysis result. When K<0.5, the regulator is unstable. High gain peaking at 0.5 results in sub-harmonic oscillation at FSW/2. When K=1, one-cycle damping is realized. Q is equal to 0.673 at this point. A higher K factor may introduce additional phase shift by moving the sampled gain inductor pole closer to the crossover frequency, but will help reduce noise sensitivity in the current loop. The maximum allowable value of K factor can be calculated by the Maximum Crossover Frequency equation in Table 1.
|DESIGN PARAMETER||EXAMPLE VALUE|
|Output Voltage VOUT||3.3 V|
|Full Load Current IOUT||9 A|
|Minimum Input Voltage VIN(MIN)||6 V|
|Maximum Input Voltage VIN(MAX)||36 V|
|Switching Frequency fSW||230 kHz|
|External VCC Supply||No|
Generally, higher frequency applications are smaller but have higher losses. Operation at 230 kHz was selected for this example as a reasonable compromise between small size and high efficiency. The value of RT for 230 kHz switching frequency can be calculated from Equation 3.
A standard value of 22.1kΩ was chosen for RT.
The maximum inductor ripple current occurs at the maximum input voltage. Typically, 20% to 40% of the full load current is a good compromise between core loss and copper loss of the inductor. Higher ripple current allows for a smaller inductor size, but places more of a burden on the output capacitor to smooth the ripple voltage on the output. For this example, a ripple current of 20% of 9A was chosen. Knowing the switching frequency, maximum ripple current, maximum input voltage and the nominal output voltage, the inductor value can be calculated as follows:
The closest standard value of 6.8μH was chosen for LO. Using the value of 6.8μH for LO, calculate IPP again. This step is necessary if the chosen value of LO differs significantly from the calculated value.
From Equation 11,
At the minimum input voltage, this value is 0.95A.
The DEMB pin is left floating since this example uses diode emulation to reduce the power loss under no load or light load conditions.
The performance of the converter will vary depending on the K value. For this example, K=1 was chosen to control sub-harmonic oscillation and achieve one-cycle damping. The maximum output current capability (IOUT(MAX)) should be 20~50% higher than the required output current, to account for tolerances and ripple current. For this example, 150% of 9A was chosen. The current sense resistor value can be calculated from Equation 9 and Equation 10 as follows:
A value of 8mΩ was chosen for RS. A larger value resistor can be placed in parallel with RS to adjust the maximum output current capability. The sense resistor must be rated to handle the power dissipation at maximum input voltage when current flows through the low-side NMOS for the majority of the PWM cycle. The maximum power dissipation of RS can be calculated as:
The worst case peak inductor current under the output short condition can be calculated from Equation 12 as follows:
Where tON(MIN) is normally 100ns.
The LM25117 itself is not affected by the large leading edge spike because it samples valley current just prior to the onset of the high-side switch. A current sense filter is used to minimize a noise injection from any external noise sources. In general, a current sense filter is not necessary. In this example, a current sense filter is not used
Adding RCS resistor changes the current sense amplifier gain which is defined as AS=10k / (1k+RCS). A small value of RCS resistor below 100Ω is recommended to minimize the gain change which is caused by the temperature coefficient difference between internal and external resistors.
The positive slope of the inductor current ramp signal is emulated by RRAMP and CRAMP. For this example, the value of CRAMP was set at the standard capacitor value of 820pF. With the inductor, sense resistor and the K factor selected, the value of RRAMP can be calculated from Equation 4 as follows:
The standard value of 105 kΩ was selected for RRAMP.
The desired startup voltage and the hysteresis are set by the voltage divider RUV1 and RUV2. Capacitor CFT provides filtering for the divider. For this design, the startup voltage was set to 5.7V, 0.3V below VIN(MIN). VHYS was set to 1V. The value of RUV1, RUV2 can be calculated from Equation 1 and Equation 2 as follows:
The standard value of 50kΩ was selected for RUV2. RUV1 was selected to be 14kΩ. A value of 100pF was chosen for CFT.
In this example, VCCDIS is left floating to enable the internal VCC regulator.
Selection of the power NMOS devices is governed by the same trade-offs as switching frequency. Breaking down the losses in the high-side and low-side NMOS devices is one way to compare the relative efficiencies of different devices. Losses in the power NMOS devices can be broken down into conduction loss, gate charging loss, and switching loss.
Conduction loss PDC is approximately:
Where D is the duty cycle and the factor of 1.3 accounts for the increase in the NMOS device on-resistance due to heating. Alternatively, the factor of 1.3 can be eliminated and the high temperature on-resistance of the NMOS device can be estimated using the RDS(ON) vs Temperature curves in the MOSFET datasheet.
Gate charging loss (PGC) results from the current driving the gate capacitance of the power NMOS devices and is approximated as:
Qg refers to the total gate charge of an individual NMOS device, and ‘n’ is the number of NMOS devices. Gate charge loss differs from conduction and switching losses in that the actual dissipation occurs in the controller IC. Switching loss (PSW) occurs during the brief transition period as the high-side NMOS device turns on and off. During the transition period both current and voltage are present in the channel of the NMOS device. The switching loss can be approximated as:
tR and tF are the rise and fall times of the high-side NMOS device. The rise and fall times are usually mentioned in the MOSFET datasheet or can be empirically observed with an oscilloscope. Switching loss is calculated for the high-side NMOS device only. Switching loss in the low-side NMOS device is negligible because the body diode of the low-side NMOS device turns on before and after the low-side NMOS device switches. For this example, the maximum drain-to-source voltage applied to either NMOS device is 36V. The selected NMOS devices must be able to withstand 36V plus any ringing from drain to source and must be able to handle at least the VCC voltage plus any ringing from gate to source.
A resistor-capacitor snubber network across the low-side NMOS device reduces ringing and spikes at the switching node. Excessive ringing and spikes can cause erratic operation and can couple noise to the output voltage. Selecting the values for the snubber is best accomplished through empirical methods. First, make sure the lead lengths for the snubber connections are very short. Start with a resistor value between 5 and 50Ω. Increasing the value of the snubber capacitor results in more damping, but higher snubber losses. Select a minimum value for the snubber capacitor that provides adequate damping of the spikes on the switch waveform at heavy load. A snubber may not be necessary with an optimized layout.
The bootstrap capacitor between the HB and SW pin supplies the gate current to charge the high-side NMOS device gate during each cycle’s turn-on and also supplies recovery charge for the bootstrap diode. These current peaks can be several amperes. The recommended value of the bootstrap capacitor is at least 0.1μF. CHB should be a good quality, low ESR, ceramic capacitor located at the pins of the IC to minimize potentially damaging voltage transients caused by trace inductance. The absolute minimum value for the bootstrap capacitor is calculated as:
Where Qg is the high-side NMOS gate charge and ΔVHB is the tolerable voltage droop on CHB, which is typically less than 5% of VCC or 0.15V conservatively. A value of 0.47μF was selected for this design.
The primary purpose of the VCC capacitor (CVCC) is to supply the peak transient currents of the LO driver and bootstrap diode as well as provide stability for the VCC regulator. These peak currents can be several amperes. The recommended value of CVCC should be no smaller than 0.47μF, and should be a good quality, low ESR, ceramic capacitor. CVCC should be placed at the pins of the IC to minimize potentially damaging voltage transients caused by trace inductance. A value of 1μF was selected for this design.
The output capacitors smooth the output voltage ripple caused by inductor ripple current and provide a source of charge during transient loading conditions. For this design example, a 680μF electrolytic capacitor with maximum 10mΩ ESR was selected as the main output capacitor. The fundamental component of the output ripple voltage with maximum ESR is approximated as:
Additional low ERS / ESL ceramic capacitors can be placed in parallel with the main output capacitor to further reduce the output voltage ripple and spikes. In this example, two 22μF capacitors were added.
The regulator input supply voltage typically has high source impedance at the switching frequency. Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the on-time. When the high-side NMOS device turns on, the current into the device steps to the valley of the inductor current waveform, ramps up to the peak value, and then drops to the zero at turnoff. The input capacitor should be selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current rating necessary is IRMS > IOUT / 2.
In this example, seven 2.2μF ceramic capacitors were used. With ceramic capacitors, the input ripple voltage will be triangular. The input ripple voltage can be approximated as:
Capacitors connected in parallel should be evaluated for RMS current rating. The current will split between the input capacitors based on the relative impedance of the capacitors at the switching frequency.
An R-C filter (RVIN, CVIN) on VIN is optional. The filter helps to prevent faults caused by high frequency switching noise injection into the VIN pin. 0.47μF ceramic capacitor is used for CVIN in the example.
The capacitor at the SS pin (CSS) determines the soft-start time (tSS), which is the time for the output voltage to reach the final regulated value. The tSS for a given CSS can be calculated from Equation 8 as follows:
For this example, a value of 0.047μF was chosen for a soft-start time of 3.8ms.
The capacitor at the RES pin (CRES) determines tRES, which is the time the LM25117 remains off before a restart attempt is made in hiccup mode current limiting. tRES for a given CRES can be calculated from Equation 13 as follows:
For this example, a value of 0.47μF was chosen for a restart time of 59ms.
RFB1 and RFB2 set the output voltage level. The ratio of these resistors is calculated as:
The ratio between RCOMP and RFB2 determines the mid-band gain, AFB_MID. A larger value for RFB2 may require a corresponding larger value for RCOMP. RFB2 should be large enough to keep the total divider power dissipation small. 3.24kΩ was chosen for RFB2 in this example, which results in a RFB1 value of 1.05kΩ for 3.3V output.
RCOMP, CCOMP and CHF configure the error amplifier gain and phase characteristics to produce a stable voltage loop. For a quick start, follow the 4 steps listed below.
STEP1: Select fCROSS
By selecting one tenth of the switching frequency, fCROSS is calculated as follows:
STEP2: Determine required RCOMP
Knowing fCROSS, RCOMP is calculated as follows:
The standard value of 27.4kΩ was selected for RCOMP
STEP3: Determine CCOMP to cancel load pole
Knowing RCOMP, CCOMP is calculated as follows:
The standard value of 10nF was selected for CCOMP
STEP4: Determine CHF to cancel ESR zero
Knowing RCOMP and CCOMP, CHF is calculated as follows:
Half of the maximum ESR is assumed as a typical ESR. The standard value of 150pF was selected for CHF.
|SIMPLE FORMULA||COMPREHENSIVE FORMULA(1)|
|Modulator Transfer Function|
|Modulator DC Gain|
|ESR Pole||Not considered|
|Dominant Load Pole|
|Sampled Gain Inductor Pole||Not considered|
|Quality Factor||Not considered|
|Sub-harmonic Double Pole||Not considered|
|Feedback Transfer Function|
|Feedback DC Gain|
|Low Frequency Zero|
|High Frequency Pole|
|Crossover Frequency (Open Loop Bandwidth)|
|Maximum Crossover Frequency||
The frequency at which 45° phase shift occurs in modulator phase characteristics.
The LM25117 can be configured as a constant current regulator by using the current monitor feature (CM) as the feedback input. A voltage divider at the VCCDIS pin from VOUT to AGND can be used to protect against output over-voltage. When the VCCDIS pin voltage is greater than the VCCDIS threshold, the controller disables the VCC regulator and the VCC pin voltage decays. When the VCC pin voltage is less than the VCC UV threshold, both HO and LO outputs stop switching. Due to the time delay required for VCC to decay below the VCC UV threshold, the over-voltage protection operates in hiccup mode. See Figure 35.
The LM25117 also can be configured as a constant voltage and constant current regulator, known as CV+CC regulator. In this configuration, there is much less variation in the current limiting as compared to peak cycle-by-cycle current limiting of the inductor current. The LMV431 and the PNP transistor create a voltage-to-current amplifier in the current loop. This amplifier circuitry does not affect the normal operation when the output current is less than the current limit set-point. When the output current is greater than the set-point, the PNP transistor sources a current into CRAMP and increases the positive slope of emulated inductor current ramp until the output current is less than or equal to the current limit set-point. See Figure 36 and Figure 37.