SNAS555D June   2000  – December 2016 LM2907-N , LM2917-N

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential Input
      2. 9.3.2 Configurable
      3. 9.3.3 Output Stage
    4. 9.4 Device Functional Modes
      1. 9.4.1 Grounded Input Devices (8-Pin LM2907 and LM2917)
      2. 9.4.2 Differential Input Devices (LM2907 and LM2917)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Minimum Component Tachometer
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Choosing R1 and C1
          2. 10.2.1.2.2 Using Zener Regulated Options (LM2917)
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Other Application Circuits
        1. 10.2.2.1 Variable Reluctance Magnetic Pickup Buffer Circuits
        2. 10.2.2.2 Finger Touch or Contact Switch
        3. 10.2.2.3 Over-Speed Latch
        4. 10.2.2.4 Frequency Switch Applications
          1. 10.2.2.4.1 Application Curves
        5. 10.2.2.5 Anti-Skid Circuits
          1. 10.2.2.5.1 Select-Low Circuit
          2. 10.2.2.5.2 Select-High Circuit
          3. 10.2.2.5.3 Select-Average Circuit
        6. 10.2.2.6 Changing the Output Voltage for an Input Frequency of Zero
        7. 10.2.2.7 Changing Tachometer Gain Curve or Clamping the Minimum Output Voltage
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

P and D Package
8-Pin PDIP and SOIC
Top View

Pin Functions: 8 Pins

PIN I/O DESCRIPTION
NAME NO.
COL 5 I The collector of the bipolar junction transistor
CP1 2 O A capacitor placed on this pin will be charged up to VCC/2 by a constant current source of 180 µA typical at the start of every positive half cycle. At the beginning of negative half cycles this capacitor is discharged the same amount at the same rate.
CP2/IN+ 3 I/O See pins CP1 and IN+. On 8-pin devices (8-pin LM2907 and LM2917) these two nodes share a pin and are internally connected.
EMIT 4 O The emitter of the bipolar junction transistor
GND — G Ground
IN+ — I The noninverting input to the high gain op amp
IN– 7 I The inverting input to the high gain op amp
NC — — No connect
TACH+ 1 I Positive terminal for the input signal that leads to the noninverting terminal of the internal Schmitt-Trigger comparator.
TACH–/GND 8 I Negative terminal for the input signal that leads to the noninverting terminal of the internal Schmitt-Trigger comparator. (NOTE: On 8-pin devices, LM2907 and LM2917, this pin is internally connected to ground and must be tied to ground externally to provide the reference voltage of the device).
V+ 6 I Supply voltage
NFF and D Package
14-Pin PDIP and SOIC
Top View

Pin Functions: 14 Pins

PIN I/O DESCRIPTION
NAME NO.
COL 8 I The collector of the bipolar junction transistor
CP1 2 O A capacitor placed on this pin will be charged up to VCC/2 by a constant current source of 180 µA typical at the start of every positive half cycle. At the beginning of negative half cycles this capacitor is discharged the same amount at the same rate.
CP2 3 O The charge pump sources current out of this pin equal to the absolute value of the capacitor current on CP1. A resistor and capacitor in parallel connected to this pin filters the current pulses into the output voltage.
EMIT 5 O The emitter of the bipolar junction transistor
GND 12 G Ground
IN+ 4 I The noninverting input to the high gain op amp
IN– 10 I The inverting input to the high gain op amp
NC 6, 7, 13, 14 — No connect
TACH+ 1 I Positive terminal for the input signal that leads to the noninverting terminal of the internal Schmitt-Trigger comparator.
TACH– 11 I Negative terminal for the input signal that leads to the noninverting terminal of the internal Schmitt-Trigger comparator.
V+ 9 I Supply voltage