SNVSCL9 March   2011  – November 2023 LM3481-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings: LM3481-Q1
    3. 5.3 Recommended Operating Ratings
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Overvoltage Protection
      2. 6.3.2 Bias Voltage
      3. 6.3.3 Slope Compensation Ramp
      4. 6.3.4 Frequency Adjust, Synchronization, and Shutdown
      5. 6.3.5 Undervoltage Lockout (UVLO) Pin
      6. 6.3.6 Short-Circuit Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Boost Converter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Custom Design with WEBENCH Tools
          2. 7.2.1.2.2  Power Inductor Selection
          3. 7.2.1.2.3  Programming the Output Voltage and Output Current
          4. 7.2.1.2.4  Current Limit With Additional Slope Compensation
          5. 7.2.1.2.5  Power Diode Selection
          6. 7.2.1.2.6  Power MOSFET Selection
          7. 7.2.1.2.7  Input Capacitor Selection
          8. 7.2.1.2.8  Output Capacitor Selection
          9. 7.2.1.2.9  Driver Supply Capacitor Selection
          10. 7.2.1.2.10 Compensation
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Typical SEPIC Converter
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Power MOSFET Selection
          2. 7.2.2.2.2 Power Diode Selection
          3. 7.2.2.2.3 Selection of Inductors L1 and L2
          4. 7.2.2.2.4 Sense Resistor Selection
          5. 7.2.2.2.5 SEPIC Capacitor Selection
          6. 7.2.2.2.6 Input Capacitor Selection
          7. 7.2.2.2.7 Output Capacitor Selection
        3. 7.2.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Custom Design with WEBENCH Tools
      2. 8.1.2 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.2.1.2.6 Power MOSFET Selection

The drive pin, DR, of the LM3481-Q1 must be connected to the gate of an external MOSFET. In a boost topology, the drain of the external N-Channel MOSFET is connected to the inductor and the source is connected to the ground. The drive pin voltage, VDR, depends on the input voltage (see Section 5.6). In most applications, a logic level MOSFET can be used. For very low input voltages, a sub-logic level MOSFET should be used.

The selected MOSFET directly controls the efficiency. The critical parameters for selection of a MOSFET are:

  • Minimum threshold voltage, VTH(MIN)
  • On-resistance, RDS(ON)
  • Total gate charge, Qg
  • Reverse transfer capacitance, CRSS
  • Maximum drain to source voltage, VDS(MAX)

The off-state voltage of the MOSFET is approximately equal to the output voltage. VDS(MAX) of the MOSFET must be greater than the output voltage. The power losses in the MOSFET can be categorized into conduction losses and ac switching or transition losses. RDS(ON) is needed to estimate the conduction losses. The conduction loss, PCOND, is the I2R loss across the MOSFET. The maximum conduction loss is given by:

Equation 36. GUID-2E545F19-F509-4390-86B2-2249E3DAF280-low.gif

where DMAX is the maximum duty cycle.

Equation 37. GUID-D94EEE69-98B5-4846-8731-D5204FD9EA8B-low.gif

At high switching frequencies the switching losses may be the largest portion of the total losses.

The switching losses are very difficult to calculate due to changing parasitics of a given MOSFET in operation. Often, the individual MOSFET datasheet does not give enough information to yield a useful result. Equation 38 and Equation 39 give a rough idea how the switching losses are calculated:

Equation 38. GUID-15876414-E32A-4750-95AC-A5985B182806-low.gif
Equation 39. GUID-650F9759-320A-4219-B640-0D60DD6A7836-low.gif