SNVSCL9 March   2011  – November 2023 LM3481-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings: LM3481-Q1
    3. 5.3 Recommended Operating Ratings
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Overvoltage Protection
      2. 6.3.2 Bias Voltage
      3. 6.3.3 Slope Compensation Ramp
      4. 6.3.4 Frequency Adjust, Synchronization, and Shutdown
      5. 6.3.5 Undervoltage Lockout (UVLO) Pin
      6. 6.3.6 Short-Circuit Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Boost Converter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Custom Design with WEBENCH Tools
          2. 7.2.1.2.2  Power Inductor Selection
          3. 7.2.1.2.3  Programming the Output Voltage and Output Current
          4. 7.2.1.2.4  Current Limit With Additional Slope Compensation
          5. 7.2.1.2.5  Power Diode Selection
          6. 7.2.1.2.6  Power MOSFET Selection
          7. 7.2.1.2.7  Input Capacitor Selection
          8. 7.2.1.2.8  Output Capacitor Selection
          9. 7.2.1.2.9  Driver Supply Capacitor Selection
          10. 7.2.1.2.10 Compensation
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Typical SEPIC Converter
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Power MOSFET Selection
          2. 7.2.2.2.2 Power Diode Selection
          3. 7.2.2.2.3 Selection of Inductors L1 and L2
          4. 7.2.2.2.4 Sense Resistor Selection
          5. 7.2.2.2.5 SEPIC Capacitor Selection
          6. 7.2.2.2.6 Input Capacitor Selection
          7. 7.2.2.2.7 Output Capacitor Selection
        3. 7.2.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Custom Design with WEBENCH Tools
      2. 8.1.2 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Layout Guidelines

Good board layout is critical for switching controllers such as the LM3481-Q1. First the ground plane area must be sufficient for thermal dissipation purposes and second, appropriate guidelines must be followed to reduce the effects of switching noise. Switch mode converters are very fast switching devices. In such devices, the rapid increase of input current combined with the parasitic trace inductance generates unwanted Ldi/dt noise spikes. The magnitude of this noise tends to increase as the output current increases. This parasitic spike noise may turn into electromagnetic interference (EMI), and can also cause problems in device performance. Therefore, care must be taken in layout to minimize the effect of this switching noise. The current sensing circuit in current mode devices can be easily effected by switching noise. This noise can cause duty cycle jitter which leads to increased spectral noise. Although the LM3481-Q1 has 250-ns blanking time at the beginning of every cycle to ignore this noise, some noise may remain after the blanking time.

The most important layout rule is to keep the AC current loops as small as possible. Figure 7-9 shows the current flow of a boost converter. The top schematic shows a dotted line which represents the current flow during on-state and the middle schematic shows the current flow during off-state. The bottom schematic shows the currents we refer to as AC currents. These currents are the most critical currents because current is changing in very short time periods. The dotted lined traces of the bottom schematic are the once to make as short as possible.

GUID-60D4979A-3F77-4846-A562-9F67E45C7331-low.gifFigure 7-9 Current Flow in a Boost Application

The PGND and AGND pins have to be connected to the same ground very close to the device. To avoid ground loop currents attach all the grounds of the system only at one point.

A ceramic input capacitor should be connected as close as possible to the Vin pin and grounded close to the GND pin.

For a layout example please see AN-2094 LM3481 SEPIC Evaluation Board (SNVA461). For more information about layout in switch mode power supplies refer to AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines (SNVA054).