SNVSCL9 March   2011  – November 2023 LM3481-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings: LM3481-Q1
    3. 5.3 Recommended Operating Ratings
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Overvoltage Protection
      2. 6.3.2 Bias Voltage
      3. 6.3.3 Slope Compensation Ramp
      4. 6.3.4 Frequency Adjust, Synchronization, and Shutdown
      5. 6.3.5 Undervoltage Lockout (UVLO) Pin
      6. 6.3.6 Short-Circuit Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Boost Converter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Custom Design with WEBENCH Tools
          2. 7.2.1.2.2  Power Inductor Selection
          3. 7.2.1.2.3  Programming the Output Voltage and Output Current
          4. 7.2.1.2.4  Current Limit With Additional Slope Compensation
          5. 7.2.1.2.5  Power Diode Selection
          6. 7.2.1.2.6  Power MOSFET Selection
          7. 7.2.1.2.7  Input Capacitor Selection
          8. 7.2.1.2.8  Output Capacitor Selection
          9. 7.2.1.2.9  Driver Supply Capacitor Selection
          10. 7.2.1.2.10 Compensation
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Typical SEPIC Converter
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Power MOSFET Selection
          2. 7.2.2.2.2 Power Diode Selection
          3. 7.2.2.2.3 Selection of Inductors L1 and L2
          4. 7.2.2.2.4 Sense Resistor Selection
          5. 7.2.2.2.5 SEPIC Capacitor Selection
          6. 7.2.2.2.6 Input Capacitor Selection
          7. 7.2.2.2.7 Output Capacitor Selection
        3. 7.2.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Custom Design with WEBENCH Tools
      2. 8.1.2 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.2.2.2.3 Selection of Inductors L1 and L2

Proper selection of the inductors L1 and L2 to maintain constant current mode requires calculations of the following parameters.

Average current in the inductors:

Equation 48. GUID-87BF2FB9-7D3D-4A81-AA9A-A5CCB69C567F-low.png
Equation 49. IL2AVE = IOUT

Peak-to-peak ripple current, to calculate core loss if necessary:

Equation 50. GUID-62FA2905-0F31-4A9E-BB5B-E8F02F845923-low.png
Equation 51. GUID-35F3E05D-D5B2-4BF5-9A6A-D03EDF0129AD-low.png

Maintaining the condition IL > ΔIL/2 to ensure continuous conduction mode yields the following minimum values for L1 and L2:

Equation 52. GUID-134EC80D-56BF-4488-89C7-C9FA70AB9CE0-low.gif
Equation 53. GUID-DDF06506-1355-4C73-B9A9-8134B7D9BA01-low.gif

Peak current in the inductor, to ensure the inductor does not saturate:

Equation 54. GUID-3AF6D2A6-BB2A-46EE-87F2-ECDA86BEE4C1-low.png
Equation 55. GUID-4FCE3636-460C-4AE7-B388-81BAEA106E1D-low.png

IL1PK must be lower than the maximum current rating set by the current sense resistor.

The value of L1 can be increased above the minimum recommended value to reduce input ripple and output ripple. However, once ΔIL1 is less than 20% of IL1AVE, the benefit to output ripple is minimal.

By increasing the value of L2 above the minimum recommendation, ΔIL2 can be reduced, which in turn will reduce the output ripple voltage:

Equation 56. GUID-68878AF6-1241-4C98-A4F6-0780604335CE-low.gif

where ESR is the effective series resistance of the output capacitor.

If L1 and L2 are wound on the same core, then L1 = L2 = L. All the equations above will hold true if the inductance is replaced by 2L.