Table 2. Backlight Control

8.3.1.1 Backlight Brightness Control

Brightness can be controlled either by the I²C brightness register, with an external PWM control, or a combination of both. BRT_MODE bits select the brightness control mode. Different brightness control modes are shown in Table 3.

When controlling brightness through I²C, registers 0x01 and 0x02 are used. Registers 0x01 and 0x02 hold the 11-bit brightness data. Register 0x02 contains the 8 MSBs, and register 0x01 contains the 3 LSBs. The LED current only transitions to the new level after a write is done to register 0x02.

When controlling brightness through I²C, setting brightness value to '0' shuts down the backlight. When controlling the brightness with PWM input, if PWM input is low for a certain period of time (24 ms typ.), the backlight shuts down. When using the combination of a PWM input and the I²C register, either option shuts down the backlight.

Figure 39. Brightness Control with
BRT_MODE bit 00

Figure 41. Brightness Control with
BRT_MODE bit 10

Figure 40. Brightness Control with
BRT_MODE bit 01

Figure 42. Brightness Control with
BRT_MODE bit 11

8.3.1.1.1 LED Current With Brightness Selection '00'

When LED brightness is controlled from the I²C brightness registers, the 11-bit brightness data directly controls the LED current in LED1 and LED2. LED mapping can be selected as either linear or exponential. When this mode is selected setting PWM input to 0 does not disable the backlight.

With exponential mapping the 11-bit code-to-current response is approximated by the equation:

Equation 1. I_LED = 50 µA × 1.003040572^{I2C BRT CODE} (for codes > 0)

This equation is valid for I²C brightness codes between 1 and 2047. Code 0 disables the backlight. Resolution achieved at the output is maximum 16-bit at low brightness levels and additional 1 bit can be achieved with the dithering resulting in up to 17-bit output resolution. Step sizes increase when the current increases with the exponential control.

Figure 43 and Figure 44 detail the exponential response of the LED current vs. brightness code. Figure 43 shows the response on a linear Y axis while Figure 44 shows the response on a log Y axis to show the low current levels at the lower codes.

Figure 43. Exponential Response of the LED Current vs Brightness Code

Figure 44. Response of the LED Current vs Brightness Code on a Log Y Axis

With linear mapping the 11-bit code to current response is approximated by the equation:

Equation 2. I_LED = 37.67 µA + 12.33 µA × I2C BRT CODE (for codes > 0)

This equation is valid for codes between 1 and 2047. Code 0 disables the backlight.

8.3.1.2 Linear Slope and Advanced Slope

Sloper smooths the transition from one brightness value to another. Slope time can be adjusted from 0 ms to 4000 ms with SLOPE[3:0] bits. Slope time is used for sloping up and down. Slope time always remains the same regardless of the amount of change in brightness. Advanced slope makes brightness changes smooth for the human eye.

Dithering function further smooths the slope by jumping between two adjacent current values. Dithering frequency can be programmed with DITHER_FREQ_SEL[3:0] bits. Dithering function can be disabled with DISABLE_DITHER bit.

Figure 45. Sloper

8.3.1.3 Mapper

The mapper block maps the digital word into current code which is set for the LED driver. The user can select whether the mapping is exponential or linear with the LINEAR_MAPPER bit.

Exponential control is tailored to the response of the human eye such that the perceived change in brightness during ramp up or ramp down is linear.

8.3.1.4 PWM Detector and PWM Input

The PWM detector block measures the duty cycle in the PWM pin. The PWM period is measured from the rising/falling edge to the next rising/falling edge. PWM edge detection can be selected as rising or falling from register 0x08 bit 7. PWM polarity can be changed with register 0x08 bit 6. The PWM input block timeout is 24 ms after the last rising edge, which should be taken into account for 0% and 100% brightness settings (for setting 100% brightness, high level of PWM input signal should be at least 24 ms). Minimum on and off times for PWM input signal are 400 ns.

PWM input resolution is defined by the PWM detector sampling rate (24 MHz typ.). Resolution depends on the input signal frequency — for example, with 10-kHz PWM input frequency the resolution is 11-bit. If a higher input frequency is used, the resolution is lower. The minimum recommended PWM frequency is 100 Hz, and maximum recommended PWM frequency is 20 kHz.

PWM hysteresis selection sets the minimum allowable change to the input. If a smaller change is detected, it is ignored. With hysteresis the constant changing between two brightness values is avoided if there is small jitter in the input signal. Hysteresis is selected with HYSTERESIS bits in register 0x08. Using a higher hysteresis setting is recommended with high PWM input frequencies.

The PWM detector is disabled in I²C brightness mode to minimize current consumption.

8.3.2.1 Headroom Voltage

Saturation voltage of the LED drivers depends on the output current setting. In order to optimize LED drive efficiency, while maintaining good LED current accuracy, the LED-driver-regulated headroom voltage (V_HR) is kept slightly above LED driver saturation voltage. To maintain good LED current accuracy with lower current settings, LED driver size is scaled down for the lower current settings (below 1/16 of max current). In order to ensure that both current sinks remain in regulation when there is a mismatch in string voltages, the boost converter output voltage is regulated based on the LED driver with lower headroom voltage. For example, if the LEDs connected to LED1 require 25 V at the programmed current, and the LEDs connected to LED2 require 25.5 V at the programmed current, the voltage at LED1 is V_HR + 0.5 V, and the voltage at LED2 is V_HR.

Figure 47. Regulated Headroom vs LED Current

8.3.2.2 Automatic Switching Frequency Shift

To take advantage of frequency vs load dependent losses, the LM3631 has an automatic frequency-select mode. In automatic frequency-select mode the switching-frequency bit is automatically changed based on the programmed LED current. The threshold (or LED Brightness Code) at which the frequency switchover occurs is programmable via the AUTOFREQ_THRESHOLD. This register contains an 8-bit code which is compared against the 8 MSB’s of the brightness code (BRT[10:3]). When BRT[10:3] > AUTOFREQ_THRESH[7:0], the Boost Frequency Select Bit is set to a ‘1’, and the device operates in high-frequency mode. When BRT[10:3] ≤ AUTOFREQ_THRESH[7:0], the Frequency Select Bit is automatically set to ‘0’, and the device operates in low-frequency mode.

When automatic frequency-select mode is disabled, the switching frequency operates at the programmed high- or low-frequency setting across the entire LED current range.

8.3.2.3 Inductor Select Bit

The LM3631 can operate with a 10-µH or 22-µH inductor. However, the LM3631 backlight boost-control loop requires adjustment of internal loop compensation parameters based on the inductance value selected for the application. This is done through the INDUCTOR bit. For 10-µH inductors, the INDUCTOR bit must be set to '1'. For a 22-µH inductor, the INDUCTOR bit should be set to ‘0’.

8.3.2.4 PI-Compensator

The LM3631 backlight boost converter internal loop-compensation parameters (SEL_I[1:0] and SEL_P[1:0]) are factory-selected to optimize performance and stability for most backlight configurations. These settings should not need adjustment. If these settings are changed, application needs to be carefully evaluated to ensure stability and performance in all operating conditions.

8.3.3.1 Overvoltage Protection (OVP) and Open-Load Fault Protection

The LM3631 provides an OVP that monitors the LED boost output voltage (V_OUT) and protects OUT and SW from exceeding safe operating voltages. The OVP threshold can be set with the I²C register bits. The OVP limit can be set to 17 V, 21 V, 25 V, or 29 V. The OVP monitor differentiates between two overvoltage conditions and responds accordingly as outlined below:

8.3.3.2 Overcurrent Protection (OCP) and Overcurrent Protection Fault

The LM3631 has 4 selectable OCP thresholds. The programmable options are 600 mA, 700 mA, 800 mA, or 900 mA. The OCP threshold is a cycle-by-cycle current limit detected in the low-side NFET. Once the threshold is reached, the NFET turns off for the remainder of the switching period.

8.3.4.1 Display Bias Power (V_POS, V_NEG, V_OREF)

A single high-efficiency boost converter provides a positive voltage rail, V_{BST_OUT}, which serves as the power rail for the LCD V_POS and V_NEG biases, as well as for an additional regulated output V_OREF. This can be used to supply the display gamma reference, V_COM and V_CS voltages.

• The V_POS output LDO, LDO_VPOS, has a programmable range from 4 V up to 6 V with 50-mV steps and can supply up to 100 mA.
• The V_NEG output, CP_VNEG, is generated from a regulated, inverting charge pump and has an adjustable range of –6 V up to –4 V with 50-mV steps and a maximum load of 80 mA. During start-up there is a minimum delay of 500 µs due to biasing the flycap.
• The V_OREF output LDO, LDO_OREF, has programmable range from 4 V to 6 V, further adjustable in 50-mV increments and can supply up to 50 mA.

The boost voltage can be selected from the an I²C register. When selecting suitable boost-output voltage, the following estimation can be used V_BST = max(V_{LDO_VPOS}, |V_{CP_VNEG}|,V_{LDO_OREF}) + 200 mV (with lower currents) or + 300 mV (with higher currents). When the device input voltage (V_IN) > sets the LCD boost output voltage, the boost voltage goes to V_IN + 100 mV.

Figure 48. LCD Boost

8.3.4.2 Display Bias Power Sequencing (V_POS, V_NEG, V_OREF, V_CONT)

The LM3631 supports configurable output power-up and power-down timing for V_POS, V_NEG, V_CONT and V_OREF. The LED current sinks can start up after the bias voltages power ok signals (or after the timeout period has elapsed (20 ms typ.)) and shuts down before the bias power-down sequence begins. The bias power-down sequence does not start until after the LED current sinks have turned off.

The trigger for the power-up sequence is either a change from logic LOW to logic HIGH on the LCD_EN pin or the Display Bias Outputs bit. The trigger for the power-down sequence is either a change from logic HIGH to logic LOW on the LCD_EN pin or the Display Bias Outputs bit. The pull-downs or pull-ups for each output, if enabled, disengage immediately upon start-up of each respective output and re-engages immediately upon shutdown of each respective output.

LDO_CONT start-up/shutdown delay has a 3-bit programmable range.

Figure 49. General LCD Bias Power Sequence Without Backlight

Figure 50. General LCD Bias Power Sequence With Backlight

8.3.4.3 Active Discharge

An active discharge is implemented for each output rail (LDO_OREF, LDO_VPOS, LDO_CONT and CP_VNEG) with internal switch resistance. The discharge function is programmable by I²C interface and is triggered by LCD_EN = “LOW”. During power-up, each output programmed to be actively discharged (at power-down) is actively discharged as long as it is not enabled internally.

8.3.4.4 LCD Bias Protection

The LM3631 provides OVP that monitors the LCD Bias boost output voltage (V_OUT) and protects BST_OUT and BST_SW from exceeding safe operating voltages. The OVP threshold can be set with the I²C register bits. If there is an LCD bias overvoltage fault, an LCD_OVPFLT fault is set. The fault is cleared with the rising edge of LCD_EN or an I²C write '1' to the LCD_OVPFLT bit.

LDO_VPOS has an OCP that limits the maximum current drawn to 200 mA (typ.). If the fault condition persists over 2 ms, the LCD is shut down according to the normal shutdown sequence, and an LDO_VPOS_FLT fault is set. The fault must be cleared to enable power; the fault is cleared with rising edge of LCD_EN or an I²C write '1' to LDO_VPOS_FLT bit.

LDO_OREF has OCP that limits the maximum current drawn to 80 mA (typ.). If the fault condition persists over 2 ms, the LCD is shut down according to the normal shutdown sequence, and an LDO_OREF_FLT fault is set. The fault must be cleared to enable powers; the fault is cleared with rising edge of LCD_EN or I²C write '1' to LDO_OREF_FLT bit.

CP_VNEG has a short-circuit and OVP feature, which monitors the charge-pump voltage.

• If the charge-pump voltage goes 250 mv (typ.) below its target set-point, the charge pump is shut down. If the OVP persists for 2 ms, all bias outputs are turned off following the normal shutdown sequence, and a NEG_CP_OVP fault is set. The fault must be cleared, to re-enable the outputs, with the rising edge of LCD_EN or an I²C write '1' to NEG_CP_OVP bit.
• If the charge-pump voltage goes over –1 V, the charge pump is shut down, and a NEG_CP_SC fault gets set. The fault must be cleared, to re-enable the outputs, with rising edge of LCD_EN or an I²C write '1' to NEG_CP_SC.

Table 8. FLAG Pin Configuration

Table 9. Power-Good Flag Configuration

8.5.1.1 Interface Bus Overview

The I²C-compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected to the bus. The two interface lines are the Serial Data Line (SDA) and the Serial Clock Line (SCL). These lines should be connected to a positive supply via a pull-up resistor and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave, depending whether it generates or receives the serial clock (SCL).

8.5.1.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock.

Figure 52. Data Validity

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software), and a Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following sections provide further details of this process.

Figure 53. Acknowledge Signal

The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start Condition is generated, the bus is considered busy, and it retains this status until a certain time after a Stop Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.

Figure 54. Start and Stop Conditions

In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed, or a register read cycle.

8.5.1.3 Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte.

8.5.1.4 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received.

There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

8.5.1.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LM3631 operates as a slave device with the 7-bit address. If an 8-bit address is used for programming, the 8th bit is '1' for read and '0' for write. The 7-bit address for the LM3631 is 0x29.

Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address — the eighth bit.

When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

Figure 55. I²C Device Address

Control Register Write Cycle

• Master device generates start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master sends data byte to be written to the addressed register.
• Slave sends acknowledge signal.
• If master sends further data bytes the control register address is incremented by one after acknowledge signal.
• Write cycle ends when the master creates stop condition.

Control Register Read Cycle

• Master device generates a start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal
• Master device generates repeated start condition.
• Master sends the slave address (7 bits) and the data direction bit (r/w = 1).
• Slave sends acknowledge signal if the slave address is correct.
• Slave sends data byte from addressed register.
• If the master device sends acknowledge signal, the control register address is incremented by one. Slave device sends data byte from addressed register.
• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition.

Figure 56. Register Write Format

When a READ function is to be accomplished, a WRITE function must precede the READ function, as show in the Read Cycle waveform.

Figure 57. Register Read Format