SNVS834 August   2014 LM3631

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements (SDA, SCL)
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Features Description
      1. 8.3.1  Backlight
        1. 8.3.1.1 Backlight Brightness Control
          1. 8.3.1.1.1 LED Current With Brightness Selection '00'
          2. 8.3.1.1.2 LED Current With Brightness Selection '01'
          3. 8.3.1.1.3 LED Current With Brightness Selections '10' and '11'
        2. 8.3.1.2 Linear Slope and Advanced Slope
        3. 8.3.1.3 Mapper
        4. 8.3.1.4 PWM Detector and PWM Input
      2. 8.3.2  Backlight Boost Converter
        1. 8.3.2.1 Headroom Voltage
        2. 8.3.2.2 Automatic Switching Frequency Shift
        3. 8.3.2.3 Inductor Select Bit
        4. 8.3.2.4 PI-Compensator
      3. 8.3.3  Backlight Protection and Faults
        1. 8.3.3.1 Overvoltage Protection (OVP) and Open-Load Fault Protection
        2. 8.3.3.2 Overcurrent Protection (OCP) and Overcurrent Protection Fault
          1. 8.3.3.2.1 Overcurrent Protection Fault Flag (BL_OCPFLT)
          2. 8.3.3.2.2 Short Circuit Fault Flag (BL_SCFLT)
      4. 8.3.4  LCD Bias
        1. 8.3.4.1 Display Bias Power (VPOS, VNEG, VOREF)
        2. 8.3.4.2 Display Bias Power Sequencing (VPOS, VNEG, VOREF, VCONT)
          1. 8.3.4.2.1 Start-Up and Shutdown Delays
          2. 8.3.4.2.2 Special Conditions During Display Bias Power Sequencing
        3. 8.3.4.3 Active Discharge
        4. 8.3.4.4 LCD Bias Protection
      5. 8.3.5  Display Controller Power (VLDO_CONT)
      6. 8.3.6  RESET Register
      7. 8.3.7  nRST Input
      8. 8.3.8  FLAG Pin
      9. 8.3.9  Power-Good Flag
      10. 8.3.10 OTP_SEL Pin
      11. 8.3.11 Thermal Shutdown
      12. 8.3.12 Undervoltage Lockout
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Serial Bus Interface
        1. 8.5.1.1 Interface Bus Overview
        2. 8.5.1.2 Data Transactions
        3. 8.5.1.3 Acknowledge Cycle
        4. 8.5.1.4 Acknowledge After Every Byte Rule
        5. 8.5.1.5 Addressing Transfer Formats
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 External Components
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Boost Output Capacitor Selection
        4. 9.2.2.4 Backlight Boost Diode Selection
        5. 9.2.2.5 Charge Pump Capacitor Selection
        6. 9.2.2.6 LDO Output Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

  • Place the boost converters output capacitors as close to the output voltage and GND pins as possible.
  • Minimize the boost converter switching loops by placing the input capacitors and inductors close to GND and switch pins.
  • If possible, route the switching loops on top layer only. For best efficiency, try to minimize copper on the switch node to minimize switch pin parasitic capacitance while preserving adequate routing width.
  • VIN input voltage pin needs to be bypassed to ground with a low-ESR bypass capacitor. Place the capacitor as close to VIN pin as possible
  • Place the output capacitors of the LDOs as close to output pins as possible. Also place the charge pump flying capacitor and output capacitor close to respective pins.
  • Route the internal pins on the second layer. Use offset micro vias to go from top layer to mid layer1. Avoid routing the signal traces directly under the switching loops of the boost converters.

11.2 Layout Example

LM3631_Pin_Diagram_With_Components.gif