SNVS480J January   2007  – July 2020 LM5022


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High-Voltage Start-Up Regulator
      2. 7.3.2 Input Undervoltage Detector
      3. 7.3.3 Error Amplifier
      4. 7.3.4 Current Sensing and Current Limiting
      5. 7.3.5 PWM Comparator and Slope Compensation
      6. 7.3.6 Soft Start
      7. 7.3.7 MOSFET Gate Driver
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Oscillator, Shutdown, and SYNC
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Switching Frequency
        2.  MOSFET
        3.  Output Diode
        4.  Boost Inductor
        5.  Output Capacitor
        6.  VCC Decoupling Capacitor
        7.  Input Capacitor
        8.  Current Sense Filter
        9.  RSNS, RS2, and Current Limit
        10. Control Loop Compensation
        11. Efficiency Calculations
          1. Chip Operating Loss
          2. MOSFET Switching Loss
          3. MOSFET and RSNS Conduction Loss
          4. Output Diode Loss
          5. Input Capacitor Loss
          6. Output Capacitor Loss
          7. Boost Inductor Loss
          8. Total Loss
          9. Efficiency
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Filter Capacitors
      2. 10.1.2 Sense Lines
      3. 10.1.3 Compact Layout
      4. 10.1.4 Ground Plane and Shape Routing
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Control Loop Compensation

The LM5022 uses peak current-mode PWM control to correct changes in output voltage due to line and load transients. Peak current-mode provides inherent cycle-by-cycle current limiting, improved line transient response, and easier control loop compensation.

The control loop is comprised of two parts. The first is the power stage, which consists of the pulse width modulator, output filter, and the load. The second part is the error amplifier, which is an op-amp configured as an inverting amplifier. Figure 17 shows the regulator control loop components.

LM5022 20212234.gifFigure 17. Power Stage and Error Amplifier

One popular method for selecting the compensation components is to create Bode plots of gain and phase for the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the regulator easy to determine. Software tools such as Excel, MathCAD, and Matlab are useful for observing how changes in compensation or the power stage affect system gain and phase.

The power stage in a CCM peak current mode boost converter consists of the DC gain, APS, a single low-frequency pole, ƒLFP, the ESR zero, ƒZESR, a right-half plane zero, ƒRHP, and a double pole resulting from the sampling of the peak current. The power stage transfer function (also called the control-to-output transfer function) can be written with Equation 42, Equation 43, and Equation 44.

Equation 42. LM5022 q_gps_nvs480.gif


  • the DC gain is defined as:
Equation 43. LM5022 20212236.gif


    Equation 44. RO = VO / IO

    The system ESR zero is calculated with Equation 45.

    Equation 45. LM5022 20212237.gif

    The low-frequency pole is calculated with Equation 46.

    Equation 46. LM5022 20212238.gif

    The right-half plane zero is calculated with Equation 47.

    Equation 47. LM5022 20212239.gif

    The sampling double-pole quality factor is calculated with Equation 48.

    Equation 48. LM5022 20212240.gif

    The sampling double corner frequency is calculated with Equation 49.

    Equation 49. ωn = π × fSW

    The natural inductor current slope is calculated with Equation 50.

    Equation 50. Sn = RSNS × VIN / L

    The external ramp slope is calculated with Equation 51.

    Equation 51. Se = 45 µA × (2000 + RS1 + RS2)] × ƒSW

    In Equation 43, DC gain is highest when input voltage and output current are at the maximum. In this example, those conditions are VIN = 16 V and IO = 500 mA.

    DC gain is 44 dB. The low-frequency pole, fP = ωP / 2π, is at 423 Hz, the ESR zero, fZ = ωZ / 2π, is at 5.6 MHz, and the right-half plane zero, ƒRHP = ωRHP / 2π, is at 61 kHz. The sampling double-pole occurs at one-half of the switching frequency. Proper selection of slope compensation (through RS2) is most evident the sampling double pole. A well-selected RS2 value eliminates peaking in the gain and reduces the rate of change of the phase lag. Gain and phase plots for the power stage are shown in Figure 18 and Figure 19.


    LM5022 20212241.gifFigure 18. Power Stage Gain and Phase
    LM5022 20212297.gifFigure 19. Power Stage Gain and Phase

    The single pole causes a rolloff in the gain of –20 dB/decade at lower frequency. The combination of the RHP zero and sampling double pole maintain the slope out to beyond the switching frequency. The phase tends towards –90° at lower frequency but then increases to –180° and beyond from the RHP zero and the sampling double pole. The effect of the ESR zero is not seen because its frequency is several decades above the switching frequency. The combination of increasing gain and decreasing phase makes converters with RHP zeroes difficult to compensate. Setting the overall control loop bandwidth to 1/3 to 1/10 of the RHP zero frequency minimizes these negative effects, but requires a compromise in the control loop bandwidth. If this loop were left uncompensated, the bandwidth would be 89 kHz and the phase margin –54°. The converter would oscillate, and therefore is compensated using the error amplifier and a few passive components.

    The transfer function of the compensation block (GEA) can be derived by treating the error amplifier as an inverting op amp with input impedance ZI and feedback impedance ZF. The majority of applications require a Type II, or two-pole one-zero amplifier, shown in Figure 17. The LaPlace domain transfer function for this Type II network is given by Equation 52.

    Equation 52. LM5022 20212243.gif

    Many techniques exist for selecting the compensation component values. The following method is based upon setting the mid-band gain of the error amplifier transfer function first and then positioning the compensation zero and pole:

    1. Determine the desired control loop bandwidth: The control loop bandwidth (ƒ0dB) is the point at which the total control loop gain (H = GPS × GEA) is equal to 0 dB. For this example, a low bandwidth of 10 kHz, or approximately 1/6th of the RHP zero frequency, is chosen because of the wide variation in input voltage.
    2. Determine the gain of the power stage at ƒ0dB: This value, A, can be read graphically from the gain plot of GPS or calculated by replacing the ‘s’ terms in GPS with ‘2 πf0dB’. For this example, the gain at 10 kHz is approximately 16 dB.
    3. Calculate the negative of A and convert it to a linear gain: By setting the mid-band gain of the error amplifier to the negative of the power stage gain at f0dB, the control loop gain equals 0 dB at that frequency. For this example, –16 dB = 0.15 V/V.
    4. Select the resistance of the top feedback divider resistor RFB2: This value is arbitrary, however, selecting a resistance between 10 kΩ and 100 kΩ leads to practical values of R1, C1, and C2. For this example, RFB2 = 20 kΩ 1%.
    5. Set Equation 55:
    6. Equation 53. R1 = A × RFB2

      For this example: R1 = 0.15 × 20000 = 3 kΩ

    7. Select a frequency for the compensation zero, ƒZ1: The suggested placement for this zero is at the low-frequency pole of the power stage, ƒLFP = ωLFP / 2π. For this example, ƒZ1 = ƒLFP = 423 Hz.
    8. Set Equation 54.
    9. Equation 54. LM5022 20212244.gif

      For this example, C2 = 125 nF

    10. Select a frequency for the compensation pole, ƒP1: The suggested placement for this pole is at one-fifth of the switching frequency. For this example, ƒP1 = 100 kHz
    11. Set Equation 55.
    12. Equation 55. LM5022 Equation_55.gif

      For this example, C1 = 530 pF

    13. Plug the closest 1% tolerance values for RFB2 and R1, then the closest 10% values for C1 and C2 into GEA and model the error amp: The open-loop gain and bandwidth of the internal error amplifier of the LM5022 are 75 dB and 4 MHz, respectively. Their effect on GEA can be modeled using Equation 56:
    14. Equation 56. LM5022 20212246.gif

      ADC is a linear gain, the linear equivalent of 75 dB is approximately 5600 V/V. C1 = 560 pF 10%, C2 = 120 nF 10%, R1 = 3.01 kΩ 1%

    15. Plot or evaluate the actual error amplifier transfer function:
    16. Equation 57. LM5022 20212247.gif
      LM5022 20212249.gifFigure 20. Overall Loop Gain and Phase
      LM5022 20212299.gifFigure 21. Overall Loop Gain and Phase
    17. Plot or evaluate the complete control loop transfer function: The complete control loop transfer function is obtained by multiplying the power stage and error amplifier functions together. The bandwidth and phase margin can then be read graphically or evaluated numerically. The bandwidth of this example circuit at VIN = 16 V is 10.5 kHz with a phase margin of 66°.
    18. Re-evaluate at the corners of input voltage and output current: Boost converters exhibit significant change in their loop response when VIN and IO change. With the compensation fixed, the total control loop gain and phase must be checked to ensure a minimum phase margin of 45° over both line and load.