SNVS480J January 2007 – July 2020 LM5022
The LM5022 uses peak current-mode PWM control to correct changes in output voltage due to line and load transients. Peak current-mode provides inherent cycle-by-cycle current limiting, improved line transient response, and easier control loop compensation.
The control loop is comprised of two parts. The first is the power stage, which consists of the pulse width modulator, output filter, and the load. The second part is the error amplifier, which is an op-amp configured as an inverting amplifier. Figure 17 shows the regulator control loop components.
One popular method for selecting the compensation components is to create Bode plots of gain and phase for the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the regulator easy to determine. Software tools such as Excel, MathCAD, and Matlab are useful for observing how changes in compensation or the power stage affect system gain and phase.
The power stage in a CCM peak current mode boost converter consists of the DC gain, APS, a single low-frequency pole, ƒLFP, the ESR zero, ƒZESR, a right-half plane zero, ƒRHP, and a double pole resulting from the sampling of the peak current. The power stage transfer function (also called the control-to-output transfer function) can be written with Equation 42, Equation 43, and Equation 44.
The system ESR zero is calculated with Equation 45.
The low-frequency pole is calculated with Equation 46.
The right-half plane zero is calculated with Equation 47.
The sampling double-pole quality factor is calculated with Equation 48.
The sampling double corner frequency is calculated with Equation 49.
The natural inductor current slope is calculated with Equation 50.
The external ramp slope is calculated with Equation 51.
In Equation 43, DC gain is highest when input voltage and output current are at the maximum. In this example, those conditions are VIN = 16 V and IO = 500 mA.
DC gain is 44 dB. The low-frequency pole, fP = ωP / 2π, is at 423 Hz, the ESR zero, fZ = ωZ / 2π, is at 5.6 MHz, and the right-half plane zero, ƒRHP = ωRHP / 2π, is at 61 kHz. The sampling double-pole occurs at one-half of the switching frequency. Proper selection of slope compensation (through RS2) is most evident the sampling double pole. A well-selected RS2 value eliminates peaking in the gain and reduces the rate of change of the phase lag. Gain and phase plots for the power stage are shown in Figure 18 and Figure 19.
The single pole causes a rolloff in the gain of –20 dB/decade at lower frequency. The combination of the RHP zero and sampling double pole maintain the slope out to beyond the switching frequency. The phase tends towards –90° at lower frequency but then increases to –180° and beyond from the RHP zero and the sampling double pole. The effect of the ESR zero is not seen because its frequency is several decades above the switching frequency. The combination of increasing gain and decreasing phase makes converters with RHP zeroes difficult to compensate. Setting the overall control loop bandwidth to 1/3 to 1/10 of the RHP zero frequency minimizes these negative effects, but requires a compromise in the control loop bandwidth. If this loop were left uncompensated, the bandwidth would be 89 kHz and the phase margin –54°. The converter would oscillate, and therefore is compensated using the error amplifier and a few passive components.
The transfer function of the compensation block (GEA) can be derived by treating the error amplifier as an inverting op amp with input impedance ZI and feedback impedance ZF. The majority of applications require a Type II, or two-pole one-zero amplifier, shown in Figure 17. The LaPlace domain transfer function for this Type II network is given by Equation 52.
Many techniques exist for selecting the compensation component values. The following method is based upon setting the mid-band gain of the error amplifier transfer function first and then positioning the compensation zero and pole:
For this example: R1 = 0.15 × 20000 = 3 kΩ
For this example, C2 = 125 nF
For this example, C1 = 530 pF
ADC is a linear gain, the linear equivalent of 75 dB is approximately 5600 V/V. C1 = 560 pF 10%, C2 = 120 nF 10%, R1 = 3.01 kΩ 1%