10.1 Layout Guidelines
To produce an optimal power solution with the LM5022, good layout and design of the PCB are as critical as component selection. The following are the several guidelines to create a good layout of the PCB, as based on Figure 14:
- Using a low-ESR ceramic capacitor, place CINX as close as possible to the VIN and GND pins of the LM5022.
- Using a low-ESR ceramic capacitor, place COX close to the load as possible of the LM5022.
- Using a low-ESR ceramic capacitor, place CF close to the VCC and GND pins of the LM5022.
- Minimize the loop area formed by the output capacitor connections (Co1, Co2) by D1 and Rsns. Make sure the cathode of D1 and Rsns are positioned next to each other, and place Co1(+) and Co1(–) close to D1 cathode and Rsns(–) respectively.
- Rsns(+) must be connected to the CS pin with a separate trace made as short as possible. This trace must be routed away from the inductor and the switch node (where D1, Q1, and L1 connect).
- Minimize the trace length to the FB pin by positioning RFB1 and RFB2 close to the LM5022.
- Route the VOUT sense path away from noisy node and connect it as close as possible to the positive side of COX.