SNVS293F December   2004  – August 2016 LM5025A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Voltage Start-Up Regulator
      2. 7.3.2  Line Undervoltage Detector
      3. 7.3.3  PWM Outputs
      4. 7.3.4  Compound Gate Drivers
      5. 7.3.5  PWM Comparator
      6. 7.3.6  Volt Second Clamp
      7. 7.3.7  Current Limit
      8. 7.3.8  Oscillator and Sync Capability
      9. 7.3.9  Feed-Forward Ramp
      10. 7.3.10 Soft Start
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Oscillator
        2. 8.2.2.2 Soft-Start Ramp Time and Hiccup Interval
        3. 8.2.2.3 Feedforward Ramp and Maximum On-Time Clamp
        4. 8.2.2.4 Dead Times
      3. 8.2.3 Application Curves
    3. 8.3 System Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Protection
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PW or NHQ Packages
16-Pin TSSOP or WSON
Top View

Pin Functions

PIN I/O DESCRIPTION APPLICATION INFORMATION
NO. NAME
1 VIN I Source input voltage Input to start-up regulator. Input range 13 V to 90 V, with transient capability to 105 V.
2 RAMP I Modulator ramp signal An external RC circuit from Vin sets the ramp slope. This pin is discharged at the conclusion of every cycle by an internal FET, initiated by either the internal clock or the V × Sec Clamp comparator.
3 CS1 I Current sense input for cycle-by-cycle limiting If CS1 exceeds 0.5 V the outputs goes into Cycle-by-Cycle current limit. CS1 is held low for 50 ns after OUT_A switches high providing leading edge blanking.
4 CS2 I Current sense input for soft restart If CS2 exceeds 0.5 V, the outputs will be disabled and a soft start commenced. The soft-start capacitor will be fully discharged and then released with a pullup current of 1 µA. After the first output pulse (when SS =1 V), the SS charge current will revert back to 20 µA.
5 TIME I Output overlap and dead-time control An external resistor (RSET) sets either the overlap time or dead time for the active clamp output. An RSET resistor connected between TIME and GND produces in-phase OUT_A and OUT_B pulses with overlap. An RSET resistor connected between TIME and REF produces out-of-phase OUT_A and OUT_B pulses with dead time.
6 REF O Precision 5-V reference output Maximum output current: 10-mA locally decouple with a 0.1-µF capacitor. Reference stays low until the VCC UV comparator is satisfied.
7 VCC P Output from the internal high voltage start-up regulator. The VCC voltage is regulated to 7.6 V. If an auxiliary winding raises the voltage on this pin above the regulation setpoint, the internal start-up regulator shuts down, reducing the IC power dissipation.
8 OUT_A O Main output driver Output of the main switch PWM output gate driver. Output capability of 3-A peak sink current.
9 OUT_B O Active Clamp output driver Output of the Active Clamp switch gate driver. Capable of 1.25-A peak sink current..
10 PGND G Power ground Connect directly to analog ground.
11 AGND G Analog ground Connect directly to power ground. For the WSON package option, the exposed pad is electrically connected to AGND.
12 SS I Soft-start control An external capacitor and an internal 20-µA current source set the soft-start ramp. The SS current source is reduced to 1 µA initially following a CS2 overcurrent event or an overtemperature event.
13 COMP I Input to the Pulse Width Modulator An internal 5-kΩ resistor pullup is provided on this pin. The external opto-coupler sinks current from COMP to control the PWM duty cycle.
14 RT I Oscillator timing resistor pin An external resistor connected from RT to ground sets the internal oscillator frequency.
15 SYNC I Oscillator UP and DOWN synchronization input The internal oscillator can be synchronized to an external clock with a frequency 20% lower than the internal oscillator’s free running frequency. There is no constraint on the maximum sync frequency.
16 UVLO I Line undervoltage shutdown An external voltage divider from the power source sets the shutdown comparator levels. The comparator threshold is 2.5 V. Hysteresis is set by an internal current source (20 µA) that is switched ON or OFF as the UVLO pin potential crosses the 2.5-V threshold.
— EP G Exposed pad, underside of the WSON package option Internally bonded to the die substrate. Connect to GND potential for low thermal impedance.