SNVSB14C April   2018  – October 2021 LM5036

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Voltage Start-Up Regulator
      2. 7.3.2  Undervoltage Lockout (UVLO)
      3. 7.3.3  Reference Regulator
      4. 7.3.4  Oscillator, Synchronized Input
      5. 7.3.5  Voltage-Mode Control
      6. 7.3.6  Primary-Side Gate Driver Outputs (LSG and HSG)
      7. 7.3.7  Half-Bridge PWM Scheme
      8. 7.3.8  Maximum Duty Cycle Operation
      9. 7.3.9  Pre-Biased Start-Up Process
        1. 7.3.9.1 Primary FETs Soft-Start Process
        2. 7.3.9.2 Synchronous Rectifier (SR) Soft-Start Process
      10. 7.3.10 Zero Duty Cycle Operation
      11. 7.3.11 Enhanced Cycle-by-Cycle Current Limiting with Pulse Matching
      12. 7.3.12 Reverse Current Protection
      13. 7.3.13 CBC Threshold Accuracy
      14. 7.3.14 Hiccup Mode Protection
      15. 7.3.15 Hiccup Mode Blanking
      16. 7.3.16 Over-Temperature Protection (OTP)
      17. 7.3.17 Over-Voltage / Latch (ON_OFF Pin)
      18. 7.3.18 Auxiliary Constant On-Time Control
      19. 7.3.19 Auxiliary On-Time Generator
      20. 7.3.20 Auxiliary Supply Current Limiting
      21. 7.3.21 Auxiliary Primary Output Capacitor Ripple
      22. 7.3.22 Auxiliary Ripple Configuration and Control
      23. 7.3.23 Asynchronous Mode Operation of Auxiliary Supply
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Input Transient Protection
        3. 8.2.2.3  Level-Shift Detection Circuit
        4. 8.2.2.4  Applications with VIN > 100-V
        5. 8.2.2.5  Applications without Pre-Biased Start-Up Requirement
        6. 8.2.2.6  UVLO Voltage Divider Selection
        7. 8.2.2.7  Over Voltage, Latch (ON_OFF Pin) Voltage Divider Selection
        8. 8.2.2.8  SS Capacitor
        9. 8.2.2.9  SSSR Capacitor
        10. 8.2.2.10 Half-Bridge Power Stage Design
        11. 8.2.2.11 Current Limit
        12. 8.2.2.12 Auxiliary Transformer
        13. 8.2.2.13 Auxiliary Feedback Resistors
        14. 8.2.2.14 RON Resistor
        15. 8.2.2.15 VIN Pin Capacitor
        16. 8.2.2.16 Auxiliary Primary Output Capacitor
        17. 8.2.2.17 Auxiliary Secondary Output Capacitor
        18. 8.2.2.18 Auxiliary Feedback Ripple Circuit
        19. 8.2.2.19 Auxiliary Secondary Diode
        20. 8.2.2.20 VCC Diode
        21. 8.2.2.21 Opto-Coupler Interface
        22. 8.2.2.22 Full-Bridge Converter Applications
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
        1. 11.2.1.1 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from Revision B (April 2019) to Revision C (October 2021)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Updated footnote to standard language.Go
  • Deleted minimum and maximum peak value of current source for slope compensation (ISLOPE) specifications. Updated typical from 54 µA to 36 µA. Removed table note (1) from this parameter.Go
  • Changed typical peak current (ISO_PRI) specification from 1.5 A to 1 A Go
  • Changed minimum BST_AUX undervoltage threshold (VBST_AUX(UVLO) ) specification from 2.1 V to 3.5 V Go
  • Changed typical BST_AUX undervoltage threshold (VBST_AUX(UVLO) ) specification from 2.8 V to 5.0 V Go
  • Changed maximum BST_AUX undervoltage threshold (VBST_AUX(UVLO) ) specification from 3.6 V to 6.5 V Go
  • Clarified footnote in Section 6.6 Go
  • Added information and clarity to Section 7.3.2(Undervoltage Lockout (UVLO)Go
  • Changed typical peak current source value references from "1.5 A" to "1 A" in Section 7.3.6 Go
  • Separated rising and falling specs to unique rowsGo

Changes from Revision A (June 2018) to Revision B (April 2019)

  • Go
  • Added minimum recommended values for RD1 and RD2 Go
  • Changed minimum recommended input voltage from 18V to 16V. Go
  • Added current limit parameters KCBC1, VCSOFFSET and IBiasOffset Go
  • Changed typical value of ISLOPE from 50-µA to 54-µA.Go
  • Added parameter names for some items that had none: IOVL, VSSSecEn, VSSREn, tCSLSG, tCSBLK, VRESTh2, VRESTh3 VRTReg, VRTSync,ICOSsrEn, IAUX(LIM) Go
  • Changed parameter name VRES to VRESTh1 Go
  • Changed parameter name VPWM-OS to IPWM-OS Go
  • Changed parameter VAUX_UVLO maximum value from 16.6V to 16V. Go
  • Changed parameter name HC_BLK_TH to VHC_BLK_TH Go
  • Added new parameters AUX SUPPLY CURRENT LIMIT: tCSBLKA, tAUX(LIM), τAuxSns Go
  • Added new conditions in Switching Characteristics for tON Go
  • Added Reference to the Calculator tool.Go
  • Changed Positive and negative current limit shown to be affected by LEB signal. Go
  • Added reference to operation from voltages above 100V. Values replaced with parameter names. Go
  • Changed Change to wording to improve clarity Go
  • Added reference to table of device functional modes.Go
  • Changed Parameter name VREF to VREFSec to avoid confusion with primary reference voltage.Go
  • Changed Implied minimum value of tD from 0-ns to 30-nsGo
  • Added note that minimum value of RD1/RD2 resistors should not be less that 5-kΩ Go
  • Added pre-biased start-up process is handled automatically by LM5036 Go
  • Changed values to parameter names. VREF changed to VREFSec, TH changed to VTHSec Go
  • Changed values to parameter names. ICOMP is graphed instead of VCOMP. Go
  • Changed VCOMP to ICOMP. Go
  • Changed and expanded Section: 'Enhanced Cycle-by-Cycle Current Limiting with Pulse Matching'.Go
  • Changed and expanded Section: 'Reverse Current Protection'. Go
  • Added Section: 'CBC Threshold Accuracy'.Go
  • Changed values to parameter names. Go
  • Changed Section: 'ON_OFF Pin' to 'Over-Voltage / Latch (ON_OFF Pin)'. Values replaced by parameter names. Go
  • Changed Section: 'Constant On-Time Control' to 'Auxiliary Constant On-Time Control'.Go
  • Changed Section: 'On-Time Generator' to 'Auxiliary On-Time Generator'.Go
  • Added method to calculate peak Auxiliary transformer current. External schottky recommended to improve Auxiliary efficiency during ASYNCH mode. Go
  • Deleted Section: 'Ripple Configuration Types'Go
  • Added Section: 'Auxiliary Ripple Configuration and Control'. Go
  • Changed values to parameter names. Go
  • Changed C26 from 330-pF to 47-pF, R29 from 165-kΩ to 220-kΩ. Added D11.Go
  • Changed voltage targets for auxiliary output voltage from 12.6 V / 9 V to 11.9 V / 8.5 V. Go
  • Added reference to Excel Calculator Tool. Go
  • Added restriction on use of TL431 to implement secondary side error amplifier.Go
  • Added reference to Power Stage Designer Tool. Go
  • Changed values to parameter names. RUV1 andRUV2 replace R1 and R2. Go
  • Changed Section: 'ON_OFF Pin Voltage Divider Selection' to 'Over Voltage / Latch (ON_OFF Pin) Voltage Divider Selection'. Go
  • Added new Section: 'Half-Bridge Power Stage Design' Go
  • Changed and expanded Section:'Current Limit' Go
  • Changed calculation of Auxiliary transformer inductance. Go
  • Changed calculated value for RON resistor. Go
  • Changed calculated value of Auxiliary primary output capacitor value. Go
  • Changed calculation of secondary output capacitor. Now uses ripple peak amplitude not peak-to-peak amplitude. Go
  • Changed calculation of Auxiliary Feedback component values. Go
  • Changed expression for ICOMP to fix error. Go
  • Changed layout diagram to include external schottky diode connected between PGND and SW_AUX pins. Go

Changes from Revision * (April 2018) to Revision A (June 2018)

  • Changed marketing status from Advance Information to initial release. Go