Synchronous rectification on the secondary side of the transformer provides higher efficiency, especially for low output voltage and high output current converter, compared to the diode rectification. The reduction of the diode forward voltage drop (0.5-V to 1.5-V) to 10-mV to 200-mV V_DS voltage for a MOSFET significantly reduces rectification losses. In a typical application, the secondary windings of the transformer can be center tapped, with the output power inductor in series with the center tap, as shown in Figure 7-5. The synchronous rectifiers (SRs) provide the ground path for the energized secondary winding and the inductor current.

Figure 7-5 Half-bridge Topology with Center-Tap Rectification

The internal SR drivers are powered by the REF regulator and each SR output is capable of sourcing 0.1-A and sinking 0.2-A peak (typical). The amplitude of the SR drivers is limited to 5-V. The 5-V SR signals enable the transfer of SR control signals across the isolation barrier either through a digital isolator or isolated gate driver. It should be noted that the actual gate sourcing and sinking currents for the SRs are provided by the secondary-side gate drivers.

The timing diagram of the four PMW signals (LSG, HSG, SR1, and SR2) with dead-times is illustrated in Figure 7-6. The main clock is generated by the internal oscillator. A delayed clock is derived by adding a delay of t_D to the main clock. t_D can be calculated from Equation 3, where RD₁ is the value of the resistor connected between RD1 pin and AGND.

Equation 3.

Figure 7-6 PWM Signal Timing Diagram

As illustrated in Figure 7-6, the rising edge of the main clock is used to turn off the SRs. Primary FET drive signal LSG/HSG is turned on at the falling edge of the delayed clock. Therefore, the dead-time between the falling edge of SR and the rising edge of the respective primary FET can be calculated from Equation 4

Equation 4.

where

• t_CLK is the pulse width of the clock which is 65 ns (typical).

The minimum achievable t₁ is dominated by the pulse width of the clock when t_D is set to minimum (30 ns).

After SR1 is turned off, the body diode of SR1 continues to carry about half the inductor current until the primary power raises the drain voltage of the SR1 and reverse biases its body diode. Ideally, dead-time t₁ would be set to the minimum time that allows the SR to turn off before the body diode starts conducting.

Power is transferred from the primary to the secondary side when the LSG is turned on. During this power transfer period, the SR2 is still turned on while the SR1 is turned off. The drain voltage of SR1 is twice the voltage of the center tap at this time. Under the normal operation, the LSG is turned off either when the RAMP signal exceeds the COMP signal or at the rising edge of the next delayed clock signal (maximum duty cycle condition), whichever comes earlier. A dead-time t₂ is inserted between the falling edge of LSG and rising edge of SR1. t₂ can be calculated from Equation 5, where RD₂ is the value of the resistor connected between RD2 pin and AGND.

Equation 5.

During the dead-time t₂, the inductor current continues to flow through the body diode of SR1. Because the body diode causes more conduction loss than the SR, efficiency can be improved by minimizing the t₂ period while maintaining sufficient margin across the entire operating conditions (component tolerances, input voltages, etc.) to prevent the cross conduction between the primary FET and SR.

During the freewheeling period where both of the primary FETs are turned off while both of the SRs are turned on, the inductor current is almost equally shared between SR1 and SR2 which effectively shorts the secondary winding of the transformer. SR2 is then turned off before HSG is turned on. The power is transferred from the primary to secondary side again when HSG is turned on. After HSG is disabled and the dead-time t₂ expires, SR1 and SR2 both conduct again during the freewheeling period.

Resistor values of no less than 5-kΩ should be connected between the RD1/RD2 pins and AGND