SNVSB14C April   2018  – October 2021 LM5036

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Voltage Start-Up Regulator
      2. 7.3.2  Undervoltage Lockout (UVLO)
      3. 7.3.3  Reference Regulator
      4. 7.3.4  Oscillator, Synchronized Input
      5. 7.3.5  Voltage-Mode Control
      6. 7.3.6  Primary-Side Gate Driver Outputs (LSG and HSG)
      7. 7.3.7  Half-Bridge PWM Scheme
      8. 7.3.8  Maximum Duty Cycle Operation
      9. 7.3.9  Pre-Biased Start-Up Process
        1. 7.3.9.1 Primary FETs Soft-Start Process
        2. 7.3.9.2 Synchronous Rectifier (SR) Soft-Start Process
      10. 7.3.10 Zero Duty Cycle Operation
      11. 7.3.11 Enhanced Cycle-by-Cycle Current Limiting with Pulse Matching
      12. 7.3.12 Reverse Current Protection
      13. 7.3.13 CBC Threshold Accuracy
      14. 7.3.14 Hiccup Mode Protection
      15. 7.3.15 Hiccup Mode Blanking
      16. 7.3.16 Over-Temperature Protection (OTP)
      17. 7.3.17 Over-Voltage / Latch (ON_OFF Pin)
      18. 7.3.18 Auxiliary Constant On-Time Control
      19. 7.3.19 Auxiliary On-Time Generator
      20. 7.3.20 Auxiliary Supply Current Limiting
      21. 7.3.21 Auxiliary Primary Output Capacitor Ripple
      22. 7.3.22 Auxiliary Ripple Configuration and Control
      23. 7.3.23 Asynchronous Mode Operation of Auxiliary Supply
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Input Transient Protection
        3. 8.2.2.3  Level-Shift Detection Circuit
        4. 8.2.2.4  Applications with VIN > 100-V
        5. 8.2.2.5  Applications without Pre-Biased Start-Up Requirement
        6. 8.2.2.6  UVLO Voltage Divider Selection
        7. 8.2.2.7  Over Voltage, Latch (ON_OFF Pin) Voltage Divider Selection
        8. 8.2.2.8  SS Capacitor
        9. 8.2.2.9  SSSR Capacitor
        10. 8.2.2.10 Half-Bridge Power Stage Design
        11. 8.2.2.11 Current Limit
        12. 8.2.2.12 Auxiliary Transformer
        13. 8.2.2.13 Auxiliary Feedback Resistors
        14. 8.2.2.14 RON Resistor
        15. 8.2.2.15 VIN Pin Capacitor
        16. 8.2.2.16 Auxiliary Primary Output Capacitor
        17. 8.2.2.17 Auxiliary Secondary Output Capacitor
        18. 8.2.2.18 Auxiliary Feedback Ripple Circuit
        19. 8.2.2.19 Auxiliary Secondary Diode
        20. 8.2.2.20 VCC Diode
        21. 8.2.2.21 Opto-Coupler Interface
        22. 8.2.2.22 Full-Bridge Converter Applications
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
        1. 11.2.1.1 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

MIN and MAX limits apply the junction temperature range of –40°C ≤ TJ ≤ 125°C. Unless otherwise specified, the following conditions apply: VIN = 48 V, RT = 25 kΩ, RD1 = RD2 = 20 kΩ, RON = 100 kΩ. No load on LSG, HSG, SR1, SR2, UVLO = 2.5 V, ON_OFF = 0 V.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
START-UP REGULATOR
VCCVCC voltageICC = 10 mA7.57.88.1V
ICC (Lim)Vcc current limitVCC = 6 V, VIN = 20 V698194mA
ICC(ext)Vcc supply currentSupply current into Vcc from an externally applied source. VCC = 9 V, FB_AUX = 0 V6.6911mA
VCC(reg)Vcc load regulationICC from 0 to 50 mA314973mV
VCC(UV)Vcc undervoltage thresholdPositive going Vcc7.47.78.0V
Negative going Vcc6.16.36.7V
VIN shutdown currentVIN = 20 V, VUVLO = 0 V, RON = 100 kΩ276580670µA
VIN = 100 V, VUVLO = 0 V, RON = 100 kΩ299600717µA
VIN start-up regulator leakageVCC = 9 V, applied externally, FB_AUX > 2 V, SS = 0 V, RON = 100 kΩ180234304µA
VOLTAGE REFERENCE REGULATOR (REF PIN)
VREFREF voltageIREF = 0 mA4.8555.15V
VREF(REG)REF load regulationIREF = 0 to 25 mA243757mV
IREF(LIM)REF current limitVREF = 4.5 V, VIN = 20 V283947mA
VREF(UV)REF undervoltage thresholdPositive going VREF4.34.54.7V
Hysteresis0.160.260.37V
UNDERVOLTAGE LOCK OUT AND SHUTDOWN (UVLO PIN)
VUVLOUVLO threshold1.2051.251.305V
IUVLOUVLO Hysteresis current152024µA
VSDInternal startup regulator enable thresholdSS = 0 V, FB_AUX = 2.5 V0.340.380.41V
Hysteresis90135175mV
OVER-VOLTAGE/LATCH (ON_OFF PIN)
VON_OFFON_OFF threshold1.181.251.32V
IOVLON_OFF hysteresis current405060µA
SOFT-START (SS PIN, SSSR PIN)
ISSSS charge currentSS = 0 V172024µA
VSSSecEnSS threshold to enable SSSR charge currentICOMP < 800 µA1.932.062.2V
SS output low voltageSinking 100 µA304857mV
SS threshold to disable switching86510001198mV
ISSSRSSSR charge currentSS > 2 V, ICOMP < 800 µA172024µA
SSSR output low voltageSinking 100 µA3038.749mV
VSSREnSSSR threshold to enable SR freewheeling pulse0.651.171.67V
CURRENT SENSE (CS_POS, CS_NEG, and CS_SET PIN)
VLIMCurrent limit setting voltage0.720.750.77V
Ratio of internal negative to positive current limit threshold0.30.580.9
tCSLSGCS to gate driver output delay6085122ns
tCSBLKCS leading-edge blanking335376ns
KCBC1(1)VLIM x (K2a X K10b - K10a)At CBC trip threshold7.287.517.81V
VCSOffset(1)VCS_POS - VCS_NEGAt CBC trip threshold-0.63-0.020.32mV
IBiasOffset(1)IBiasPOS - IBiasNEGAt CBC trip threshold-0.670.020.29µA
ISLOPEPeak value of current source for slope compensation

36

µA
REVERSE CURRENT PROTECTION
NNumber of switching periods to reset negative over-current event counter4
SR_CTR_THSSSR threshold to reset SSSR cap clamp event counter4.84.945.1V
HICCUP MODE (RES PIN)
RRESRES pulldown resistanceTermination of hiccup timer243655Ω
VRESTh1RES hiccup threshold0.9011.04V
VRESTh3RES upper counter threshold3.9144.07V
VRESTh2RES lower counter threshold1.9522.04V
IRES-SRC1Charge current source1VRES < 1 V, CBC active121518µA
IRES-SRC2Charge current source21 V < VRES< 4 V253036µA
IRES-DIS1Discharge current source1CBC not active3.255.5µA
IRES-DIS2Discharge current source22 V < VRES < 4 V2.557.5µA
HICCUP MODE BLANKING
VHC_BLK_THSSSR threshold to disable the hiccup blanking5.265.55.66V
VOLTAGE FEED-FORWARD (RAMP PIN)
RAMP sink impednace (clocked)3.96.09.1Ω
OSCILLATOR (RT PIN)
fSW1Frequency (half oscillator frequency)RT = 25 kΩ185200215kHz
fSW2Frequency (half oscillator frequency)RT = 10 kΩ420480540kHz
VRTRegDC level1.8522.06V
VRTSyncRT sync threshold2.833.3V
SYNCHRONOUS RECTIFIER TIMING CONTROL (RD1 and RD2 PINS)
t1SR trailing edge delay SR turn-off to primary switch turn-onRD1 = 20 kΩ94123157ns
RD1 = 100 kΩ213278350ns
t2SR leading edge delay primary switch turn-off to SR turn-onRD2 = 20 kΩ6079102ns
RD2 = 100 kΩ188250315ns
tclkPulse width of the clock476587ns
COMP PIN
IPWM-OSCOMP current to RAMP offsetRAMP = 0 V5968001063µA
VSS-OSSS to RAMP offsetRAMP = 0 V0.8611.15V
COMP current to RAMP gaindelta RAMP/delta ICOMP189524002936Ω
SS to RAMP gaindelta SS/delta RAMP0.5740.6460.74
ICOSsrEnCOMP current for SSSR charge curent enableSS > 2 V600750900µA
COMP to gate driver output delay100120150ns
Minimum duty cycleICOMP = 1 mA0%
BOOST (BST PIN)
VBST(UV)BST under-voltage thresholdVBST - VSW rising3.24.1375.6V
Hysteresis0.370.4810.65V
LSG, HSG GATE DRIVERS
VOL_PRILow-state output voltageIHSG/LSG = 100 mA0.10.30.41V
VOH_PRIHigh-state output voltageIHSG/LSG = 100 mA, VOHL_PRI = VCC - VLSG, VOHH_PRI = VBST - VHSG00.381V
Rise TimeC-load =1000 pF2812ns
Fall TimeC-load =1000 pF21014ns
ISO_PRIPeak Source CurrentVHSG/LSG = 0V1A
ISI_PRIPeak Sink CurrentVHSG/LSG = VCC2A
SR1, SR2 GATE DRIVERS
VOL_SRLow-state output voltageISR1/SR2 = 10 mA0.12V
VOH_SRHigh-state output voltageISR1/SR2 = 10 mA, VOH_SR = VREF - VSR0.313V
Rise TimeC-load = 1000 pF254565ns
Fall TimeC-load = 1000 pF41016ns
ISO_SRPeak Source CurrentVSR = 0 V0.050.090.14A
ISI_SRPeak Sink CurrentVSR = VREF0.10.20.4A
HALF BRIDGE THERMAL SHUTDOWN
TSDThermal Shutdown Temp150°C
Thermal Shutdown Hysteresis25°C
AUX SUPPLY SWITCH CHARACTERISTICS
Buck Switch RDS(ON)ITEST= 60 mA3.05.27.5Ω
Synchronous Switch RDS(ON)ITEST= 60 mA1.22.84.5Ω
AUX SUPPLY UNDERVOLTAGE LOCKOUT
VBST_AUX(UV)BST_AUX undervoltage thresholdVBST_AUX - VSW_AUX rising

3.5

5.0

6.5

V
VAUX_UVLOAUX supply UVLO input voltage rising threshold12.21516.0V
AUX supply UVLO input voltage falling threshold7.911.212.7V
AUX SUPPLY REGULATION
VAUX-OFFOFF-State AUX Voltage Regulation Level1.261.41.53V
VAUX-ONON-State AUX Voltage Regulation Level0.9511.04V
AUX SUPPLY CURRENT LIMIT
IAUX(LIM)AUX Supply Current Limit Threshold150200250mA
tCSBLKACurrent limit comparator blanking period measured from start of tON period (1)50ns
tAUX(LIM)Delay from Comparator Threshold to upper MOSFET turn-OFF (1)116ns
τAuxSnsAux Current Limit Parasitic Filter time constant (1)41ns
AUX SUPPLY THERMAL SHUTDOWN
TSD_AUXAUX Supply Thermal Shutdown Temp160°C
AUX Supply Thermal Shutdown Hysteresis28°C
Specified by design. Not production tested.