SNVS703H February   2011  – November 2014 LM5046

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Voltage Start-Up Regulator
      2. 7.3.2  Line Undervoltage Detector
      3. 7.3.3  Overvoltage Protection
      4. 7.3.4  Reference
      5. 7.3.5  Oscillator, Sync Input
      6. 7.3.6  Cycle-by-Cycle Current Limit
      7. 7.3.7  Hiccup Mode
      8. 7.3.8  PWM Comparator
      9. 7.3.9  RAMP Pin
      10. 7.3.10 Slope Pin
      11. 7.3.11 Soft-Start
      12. 7.3.12 Gate Driver Outputs
      13. 7.3.13 Synchronous Rectifier Control Outputs (SR1 & SR2)
      14. 7.3.14 Soft-Start of the Synchronous Rectifiers
      15. 7.3.15 Pre-Bias Startup
      16. 7.3.16 Soft-Stop
      17. 7.3.17 Soft-Stop Off
      18. 7.3.18 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Control Method Selection
      2. 7.4.2 Voltage Mode Control Using the LM5045
      3. 7.4.3 Current Mode Control Using the LM5045
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Phase-Shifted Full-Bridge Operation
          1. 8.2.2.1.1 Operating State 1 (Power Transfer/Active Mode)
          2. 8.2.2.1.2 Operating State 2 (Active to Passive Transition)
          3. 8.2.2.1.3 Operating State 3 (Freewheel/Passive Mode)
          4. 8.2.2.1.4 Operating State 4 (Passive to Active Transition)
        2. 8.2.2.2  Control Method Selection
        3. 8.2.2.3  Voltage Mode Control Using the LM5046
        4. 8.2.2.4  Current Mode Control Using the LM5046
        5. 8.2.2.5  VIN and VCC
        6. 8.2.2.6  For Applications With > 100 V Input
        7. 8.2.2.7  UVLO and OVP Voltage Divider Selection
        8. 8.2.2.8  Current Sense
        9. 8.2.2.9  Hiccup Mode Current Limit Restart
        10. 8.2.2.10 Augmenting the Gate Drive Strength
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The LM5046 current sense and PWM comparators are very fast and respond to short duration noise pulses. The components at the CS, COMP, SLOPE, RAMP, SS, SSSR, RES, UVLO, OVP, RD1, RD2, and RT pins should be physically close as possible to the IC, thereby minimizing noise pickup on the PC board trace inductance. Eliminating or minimizing via’s in these critical connections are essential. Layout consideration is critical for the current sense filter. If a current sense transformer is used, both leads of the transformer secondary should be routed to the sense filter components and to the IC pins. The ground side of the transformer should be connected via a dedicated PC board trace to the AGND pin, rather than through the ground plane. If the current sense circuit employs a sense resistor in the drive transistor source, low inductance resistors should be used. In this case, all the noise sensitive, low-current ground trace should be connected in common near the IC, and then a single connection made to the power ground (sense resistor ground point).

The gate drive outputs of the LM5046 should have short, direct paths to the power MOSFETs in order to minimize inductance in the PC board. The boot-strap capacitors required for the high side gate drivers should be located very close to the IC and connected directly to the BST and HS pins. The VCC and REF capacitors should also be placed close to their respective pins with short trace inductance. Low ESR and ESL ceramic capacitors are recommended for the boot-strap, VCC and the REF capacitors. The two ground pins (AGND, PGND) must be connected together directly underneath the IC with a short, direct connection, to avoid jitter due to relative ground bounce.

10.2 Layout Example

layoutcomp_snvs699.gifFigure 38. Layout of Components Around RAMP, CS, SLOPE, COMP, RT, RD1, RD2, RES, SS, and SSR
layoutcomp2_snvs699.gifFigure 39. Layout of Components Around VIN, VCC, AGND, PGND UVLO, OVP, REF, BST1, BST2, HS1, and HS2