SNVS725I June   2011  – October 2019 LM5113

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and Output
      2. 7.3.2 Start-Up and UVLO
      3. 7.3.3 HS Negative Voltage and Bootstrap Supply Voltage Clamping
      4. 7.3.4 Level Shift
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD Bypass Capacitor
        2. 8.2.2.2 Bootstrap Capacitor
        3. 8.2.2.3 Power Dissipation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Specifications are TJ = 25°C. Unless otherwise specified: VDD = VHB = 5 V, VSS = VHS = 0 V.
No load on LOL and HOL or HOH and HOL(1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IDD VDD quiescent current LI = HI = 0 V TJ = 25°C 0.07 mA
TJ = –40°C to 125°C 0.1
IDDO VDD operating current f = 500 kHz TJ = 25°C 2.0 mA
TJ = –40°C to 125°C 3.0
IHB Total HB quiescent current LI = HI = 0 V TJ = 25°C 0.08 mA
TJ = –40°C to 125°C 0.1
IHBO Total HB operating current f = 500 kHz TJ = 25°C 1.5 mA
TJ = –40°C to 125°C 2.5
IHBS HB to VSS quiescent current HS = HB = 100 V TJ = 25°C 0.1 µA
TJ = –40°C to 125°C 8
IHBSO HB to VSS operating current f = 500 kHz TJ = 25°C 0.4 mA
TJ = –40°C to 125°C 1.0
INPUT PINS
VIR Input voltage threshold Rising edge TJ = 25°C 2.06 V
TJ = –40°C to 125°C 1.89 2.18
VIF Input voltage threshold Falling edge TJ = 25°C 1.66 V
TJ = –40°C to 125°C 1.48 1.76
VIHYS Input voltage hysteresis 400 mV
RI Input pulldown resistance TJ = 25°C 200 kΩ
TJ = –40°C to 125°C 100 300
UNDERVOLTAGE PROTECTION
VDDR VDD rising threshold TJ = 25°C 3.8 V
TJ = –40°C to 125°C 3.2 4.5
VDDH VDD threshold hysteresis 0.2 V
VHBR HB rising threshold TJ = 25°C 3.2 V
TJ = –40°C to 125°C 2.5 3.9
VHBH HB threshold hysteresis 0.2 V
BOOTSTRAP DIODE
VDL Low-current forward voltage IVDD-HB = 100 µA TJ = 25°C 0.45 V
TJ = –40°C to 125°C 0.65
VDH High-current forward voltage IVDD-HB = 100 mA TJ = 25°C 0.90 V
TJ = –40°C to 125°C 1.00
RD Dynamic resistance IVDD-HB = 100 mA TJ = 25°C 1.85 Ω
TJ = –40°C to 125°C 3.60
HB-HS clamp Regulation voltage TJ = 25°C 5.2 V
TJ = –40°C to 125°C 4.7 5.45
LOW- AND HIGH-SIDE GATE DRIVER
VOL Low-level output voltage IHOL = ILOL = 100 mA TJ = 25°C 0.06 V
TJ = –40°C to 125°C 0.10
VOH High-level output voltage
VOH = VDD – LOH
or VOH = HB – HOH		 IHOH = ILOH = 100 mA TJ = 25°C 0.21 V
TJ = –40°C to 125°C 0.31
IOHL Peak source current HOH, LOH = 0 V 1.2 A
IOLL Peak sink current HOL, LOL = 5 V 5 A
IOHLK High-level output leakage current HOH, LOH = 0 V TJ = –40°C to 125°C 1.5 µA
IOLLK Low-level output leakage current HOL, LOL = 5 V TJ = –40°C to 125°C 1.5 µA