SNVSAE3B March 2016 – November 2017 LM5161
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LM5161 is a synchronousbuck regulator converter designed to operate over a wide input voltage and output current range. Spreadsheet based QuickStart Calculator tools, available on the www.ti.com product website, can be used to design a single output synchronous buck converter or an isolated dual output FlyBuck converter using the LM5161. See application note Designing an Isolated Buck (FlyBuck) Converter for a detailed design guide for the FlyBuck converter. Alternatively, the online WEBENCH® Tool can be used to create a complete buck or FlyBuck designs and generate the bill of materials, estimated efficiency, solution size, and cost of the complete solution.Typical Applications describes a few application circuits using the LM5161 with detailed, stepbystep design procedures.
A typical application example is a synchronous buck converter operating from a wide input voltage range of 15 V to 95 V and providing a stable 12 V output voltage with maximum output current capability of 1 A. The complete schematic for a typical buck application circuit with LM5161 in diode emulation is shown in Figure 25 . In the application schematic below, the components are labeled by their respective component numbers instead of the descriptive name used in the previous sections. For example, R1 represents R_{ON} and so on.
A typical synchronousbuck application introduced in LM5161 Synchronous Buck (15V to 95V Input, 12V Output, 1A Load) , Table 3 summarizes the operating parameters:
DESIGN PARAMETER  EXAMPLE VALUE 

Input voltage range  15V to 80V 
output  12V 
Full load current  1A 
Nominal switching frequency  300 kHz 
Light load operating mode  CCM, FPWM=1 
Jumper JP1  Pins 12 connected 
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With the required output voltage set point at 12 V and V_{FB} = 2 V (typical), the ratio of R8 (R_{FB1}) to R7 (R_{FB2}) can be calculated using Equation 6:
The resistor ratio calculates to be 5:1. Standard values of R8 (R_{FB1}) = 2 kΩ and R7 (R_{FB2} ) =10 kΩ are chosen. Higher or lower resistor values could be used as long as the ratio of 5:1 is maintained.
The duty cycle required to maintain output regulation at the minimum input voltage restricts the maximum switching frequency of LM5161. The maximum value of the minimum forced OFFtime T_{OFF,min} (max), limits the duty cycle and therefore the switching frequency. The maximum frequency that avoids output dropout at minimum input voltage can be calculated from Equation 7.
For this design example, the maximum frequency based on the minimum OFFtime limitation for T_{OFF,min}(typ) = 170 ns is calculated to be F_{SW,max(@VIN,min)} = 1.2 MHz. This value is above 1 MHz, the maximum possible operating frequency of the LM5161. Therefore, the minimum OFFtime parameter restricts the maximum achievable switching frequency calculation in this application.
At the maximum input voltage, the maximum switching frequency of LM5161 is restricted by the minimum ONtime, T_{ON,min} which limits the minimum duty cycle of the converter. The maximum frequency at maximum input voltage can be calculated using Equation 8.
Using Equation 8 and T_{ON,min} (typ) = 150 ns, the maximum achievable switching frequency is F_{SW,max(@VIN,min)}= 1000 kHz. Taking this value as the maximum possible operational switching frequency over the input voltage range in this application, a nominal switching frequency of F_{SW} = 300 kHz is chosen for this design.
The value of the resistor, R_{ON} sets the nominal switching frequency based on Equation 9.
For this particular application with F_{SW} = 300 kHz, R_{ON} calculates to be 396 kΩ . Selecting a standard value for R1 (R_{ON}) = 402 kΩ (±1%) results in a nominal frequency of 296 kHz. The resistor value may need to adjusted further in order to achieve the required switching frequency as the switching frequency in Constant ONTime converters varies slightly(±10%) with input voltage and/or output current. Operation at a lower nominal switching frequency will result in higher efficiency but increase in the inductor and capacitor values leading to a larger total solution size.
The inductor is selected to limit the inductor ripple current to a value between 20 and 40 percent of the maximum load current. The minimum value of the inductor required in this application can be calculated from Equation 10:
Based on Equation 10 , the minimum value of the inductor is calculated to be 85 µH for V_{IN} = 80V (max) and inductor current ripple will be 40 percent of the maximum load current. Allowing some margin for inductance variation and inductor saturation, a higher standard value of L1 (L) = 100 µH is selected for this design.
The peak inductor current at maximum load must be smaller than the minimum current limit threshold of the high side FET as given in Electrical Characteristics table. The inductor current ripple at any input voltage is given by:
The peaktopeak inductor current ripple is calculated to be 81 mA and 341 mA at the minimum and maximum input voltages respectively. The maximum peak inductor current in the buck FET is given by Equation 12:
In this design with maximum output current of 1A, the maximum peak inductor current is calculated to be approximately 1.17 A at V_{IN,max} = 80 V, which is less than the minimum highside FET current limit threshold.
The saturation current of the inductor must also be carefully considered. The peak value of the inductor current will be bound by the high side FET current limit during overload or short circuit conditions. Based on the high side FET current limit specification in the Electrical Characteristics, an inductor with saturation current rating above 1.9 A (max) should be selected.
The output capacitor is selected to limit the capacitive ripple at the output of the regulator. Maximum capacitive ripple is observed at maximum input voltage. The output capacitance required for a ripple voltage ∆V_{O} across the capacitor is given by Equation 13.
Substituting ∆V_{O, ripple} = 10 mV gives C_{OUT} = 15 μF. Two standard 10 μF ceramic capacitors in parallel (C11, C12) are selected. An X7R type capacitor with a voltage rating 25 V or higher should be used for C_{OUT} (C11, C12) to limit the reduction of capacitance due to dc bias voltage.
If the FPWM = 1, i.e. the FPWM pin is pulled high as when connected to V_{CC}, a series resistor in series with the output capacitor or the external ripple injection circuit must be selected such that sufficient ripple injection (> 25mV) is ensured at the feedback pin FB. The ripple produced by R_{ESR} is proportional to the inductor current ripple, and therefore, R_{ESR} should be chosen for minimum inductor current ripple which occurs at minimum input voltage. The R_{ESR} is calculated by Equation 14.
With V_{O} = 12 V, V_{REF} = 2 V and ΔI_{L, min} = 81 mA (at V_{IN, min}= 15 V) as calculated in Equation 11, Equation 14 requires an R_{ESR} greater than or equal to 1.87 Ω. Selecting R4 (R_{ESR}) = 2 Ω results in approximately 700 mV of maximum output voltage ripple at V_{IN,max}. However due to the internal DC Error correction loop, the load and line regulation will be much improved, despite the addition of a large R_{ESR} in the circuit. For applications which require even lower output voltage ripple, Type 2 or Type 3 ripple injection circuits must be used, as described in Ripple Configuration. In this design example, with the FPWM =1 (i.e. the FPWM pin is pulled up to V_{CC}) a 0 Ω ESR resistor is selected and the external Type 3 ripple injection circuit is used.
The VCC capacitor charges the bootstrap capacitor during the OFFtime of the highside switch and powers internal logic circuits and the low side sync FET gate driver. The bootstrap capacitor biases the highside gate driver during the highside FET ONtime. A good value for C13 (C_{VCC}) is 1 µF. A good choice for C1 (C_{BST}) is 10 nF. Both must be high quality X7R ceramic capacitors.
The input capacitor must be large enough to limit the input voltage ripple to an acceptable level. Equation 15 provides the input capacitance C_{IN} required for a worst case input ripple of ∆V_{IN, ripple}.
C_{IN} (C4, C6) supplies most of the switch current during the ONtime to limit the voltage ripple at the VIN pin. At maximum load current, when the buck switch turns on, the current into the VIN pin quickly increases to the valley current of the inductor ripple and then ramps up to the peak of the inductor ripple during the ONtime of the highside FET. The average current during the ONtime is the output load current. For a worstcase calculation, C_{IN} must supply this average load current during the maximum ONtime, without letting the voltage at VIN drop more than the desired input ripple. For this design, the input voltage drop is limited to 0.5 V and the value of C_{IN} is calculated using Equation 15.
Based on Equation 15, the value of the input capacitor is calculated to be approximately 1.68 µF at D = 0.5. Taking into account the decrease in capacitance over an applied voltage, two standard value ceramic capacitors of 2.2 μF are selected for C4 and C6. The input capacitors should be rated for the maximum input voltage under all operating and transient conditions. A 100V, X7R dielectric was selected for this design.
A third input capacitor C5 is needed in this design as a bypass path for the high frequency component of the input switching current. The value of C5 is 0.1 μF and this bypass capacitor must be placed directly across VIN and PGND (pin 3 and 2) near the IC. The C_{IN} values and location are critical to reducing switching noise and transients.
The capacitor at the SS pin determines the softstart time, that is the time for the output voltage to reach its final steady state value. The capacitor value is determined from Equation 16:
With C9 (C_{SS}) set at 22 nF and the Vss = 2 V, I_{SS} = 10 µA, the T_{Startup} should measure approximately 4 ms.
The UVLO resistors R3 (R_{UV2}) and R9 (R_{UV1}) set the input undervoltage lockout threshold and hysteresis according to Equation 17 and Equation 18:
and,
From the Electrical Characteristics, I_{UVLO(HYS)} = 20 μA (typical). To design for V_{IN} rising threshold (V_{IN, UVLO(rising)}) at 15 V and EN/UVLO hysteresis of 1.5 V, Equation 17 and Equation 18 yield R_{UV1} = 6.81 kΩ and R_{UV2} = 75 kΩ . Selecting 1% standard value of R9 (R_{UV1}) = 6.81 kΩ and R3 (R_{UV2}) = 75 kΩ results in UVLO threshold (rising) and hysteresis of 14.9 V and 1.5 V respectively.
A typical application example for an isolated FlyBuck converter operates over an input voltage range of 36 V to 72 V. It provides a stable 12 V isolated output voltage with output power capability of 10 W. The complete schematic of the FlyBuck application circuit is shown in Figure 34.
The LM5161 FlyBuck application example is designed to operate from a nominal 48V DC supply with line variations from 36V to 72V. This example provides a spaceoptimized and efficient 12V isolated output solution with secondary load current capability from 0A to 800 mA. The primary side remains unloaded in this application. The switching frequency is set at 300 kHz (nominal). This design achieves greater than 88% peak efficiency.
DESIGN PARAMETER  EXAMPLE VALUE 

Input voltage range  36 V  72 V 
Isolated output  12 V (+/ 10%) 
Isolated load current range (I_{ISO})  0A to 0.8A 
Nominal switching frequency  300 KHz 
Peak efficiency  ~87% 
Operation mode  FPWM = 1 
The FlyBuck converter design procedure closely follows the buck converter design outlined in LM5161 Synchronous Buck (15V to 95V Input, 12V Output, 1A Load). The selection of primary output voltage, transformer turns ratio, rectifier diode, and output capacitors are covered here.
The primary output voltage in a FlyBuck converter should be no more than one half of the minimum input voltage. Therefore, at the minimum V_{IN} of 36 V, the primary output voltage ( V_{OUT} ) should be no higher than 18 V. The isolated output voltage of V_{OUTISO }in Figure 34 is set at 12 V by selecting a transformer with a turns ratio (N_{1}:N_{2} :: N_{PRI}:N_{SEC}) of 1:1. Using this turns ratio, the required primary output voltage V_{OUT} is calculated in Equation 19:
The 0.7 V (V_{FD1}) added to V_{OUTISO} in Equation 19 represents the forward voltage drop of the secondary rectifier diode. By setting the primary output voltage V_{OUT} to 12.7V by selecting the correct feedback resistors, the secondary voltage is regulated at 12V nominally. Adjustment of the primary side V_{OUT} may be required to compensate for voltage errors due to the leakage inductance of the transformer, the resistance of the transformer windings, the diode drop in the power path on the secondary side and the lowside FET of the LM5161.
The secondary side rectifier diode must block the maximum input voltage reflected at secondary side switch node. The minimum diode reverse voltage V_{(RD1)} rating is given in Equation 20:
A diode of 100V or higher reverse voltage rating must be selected in this application. If the input voltage (V_{IN}) has transients above the normal operating maximum input voltage of 72 V, then the worstcase transient input voltage must be used in the Equation 20 while selecting the secondary side rectifier diode.
The FPWM pin in the LM5161 should never be grounded or left open when used in a FlyBuck application. Type 3 ripple circuit is required for FlyBuck applications. Follow the design procedure used in the buck converter for selecting the Type 3 ripple injection components. See Ripple Configuration for ripple design information.
The FlyBuck output capacitor conducts higher ripple current than a buck converter output capacitor. The ripple voltage across the isolated output capacitor is calculated based on the time the rectifier diode is off. During this time the entire output current is supplied by the output capacitor. The required capacitance for the worstcase ripple voltage can be calculated using Equation 21 where, ΔV_{ISO} is the expected ripple voltage at the secondary output.
Equation 21 is an approximation and ignores the ripple components associated with ESR and ESL of the output capacitor. For a ΔV_{ISO} = 100 mV, Equation 21 requires C_{VISO} = 11.12 µF. When selecting the C_{VISO} output capacitors (C2 and C3 in the Figure 34), the DC bias must be considered in order to ensure sufficient capacitance over the output voltage.
LM5161 uses a ConstantOnTime (COT) control scheme, in which the ONtime is terminated by a oneshot, and the OFFtime is terminated by the feedback voltage (V_{FB}) falling below the reference voltage. Therefore, for stable operation, the feedback voltage must decrease monotonically and in phase with the inductor current during the OFFtime. Furthermore, this change in feedback voltage (V_{FB}) during OFFtime must be large enough to dominate any noise present at the feedback node.
Table 5 presents three different methods for generating appropriate voltage ripple at the feedback node. Type 1 and Type 2 ripple circuits couple the ripple from the output of the converter to the feedback node (FB). The output voltage ripple has two components:
The capacitive ripple is outofphase with the inductor current. As a result, the capacitive ripple does not decrease monotonically during the OFFtime. The resistive ripple is in phase with the inductor current and decreases monotonically during the OFFtime. The resistive ripple must exceed the capacitive ripple at output (V_{OUT}) for stable operation. If this condition is not satisfied unstable switching behavior is observed in COT converters, with multiple ONtime bursts in close succession followed by a long OFFtime.
Type 3 ripple method uses a ripple injection circuit with R_{A}, C_{A} and the switch node (SW) voltage to generate a triangular ramp. This triangular ramp is then ACcoupled into the feedback node (FB) using the capacitor C_{B}. Because this circuit does not use the output voltage ripple, it is suited for applications where low output voltage ripple is imperative. See application note Controlling Output Ripple and Achieving ESR Independence in Constant OnTime (COT) Regulator Designs for more details for each ripple generation method.
TYPE 1  TYPE 2  TYPE 3 

Lowest Cost  Reduced Ripple  Minimum Ripple 



Equation 22.

Equation 23.

Equation 24.

As mentioned earlier in SoftStart , the SS capacitor C_{SS}, must be more than 1 nF in both Buck and FlyBuck applications. Apart from determining the startup time, this capacitor serves for the external compensation of the internal G_{M} error amplifier. A minimum value of 1 nF is necessary to maintain stability. The SS pin must not be left floating.
When the FPWM pin is shorted to ground or left unconnected, no external ripple injection is necessary in a Buck application. Should an external feedback ripple circuit be configured when FPWM = 0, it will produce higher ripple at the output.
Add a resistor (>3Ω) in series with the BST capacitor when using the part in FPWM = 0, as described in detail in Forced Pulse Width Modulation (FPWM) Mode.
When configured as a FlyBuck, the FPWM pin must always be connected to VCC. A FlyBuck application must operate in the continuous conduction mode all the time in order to maintain adequate voltage regulation on the secondary side. FPWM = 0 is not a valid mode in the FlyBuck application.