SNVSAE3B March   2016  – November 2017 LM5161


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Control Circuit
      2. 7.3.2  VCC Regulator
      3. 7.3.3  Regulation Comparator
      4. 7.3.4  Soft-Start
      5. 7.3.5  Error Transconductance (GM) Amplifier
      6. 7.3.6  On-Time Generator
      7. 7.3.7  Current Limit
      8. 7.3.8  N-Channel Buck Switch and Driver
      9. 7.3.9  Synchronous Rectifier
      10. 7.3.10 Enable / Undervoltage Lockout (EN/UVLO)
      11. 7.3.11 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Pulse Width Modulation (FPWM) Mode
      2. 7.4.2 Undervoltage Detector
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 LM5161 Synchronous Buck (15-V to 95-V Input, 12-V Output, 1-A Load)
        1. Design Requirements
        2. Detailed Design Procedure
          1.  Custom Design With WEBENCH® Tools
          2.  Output Resistor Divider Selection
          3.  Frequency Selection
          4.  Inductor Selection
          5.  Output Capacitor Selection
          6.  Series Ripple Resistor - RESR (FPWM = 1)
          7.  VCC and Bootstrap Capacitor
          8.  Input Capacitor Selection
          9.  Soft-Start Capacitor Selection
          10. EN/UVLO Resistor Selection
        3. Application Curves
      2. 8.2.2 LM5161 Isolated Fly-Buck (36-V to 72-V Input, 12-V, 12-W Isolated Output)
        1. LM5161 Fly-Buck Design Requirements
        2. Detailed Design Procedure
          1. Selection of VOUT and Turns Ratio
          2. Secondary Rectifier Diode
          3. External Ripple Circuit
          4. Output Capacitor (CVISO)
        3. Application Curves
      3. 8.2.3 Ripple Configuration
    3. 8.3 Do's and Don'ts
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Custom Design With WEBENCH® Tools
    2. 11.2 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Applications and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The LM5161 is a synchronous-buck regulator converter designed to operate over a wide input voltage and output current range. Spreadsheet based Quick-Start Calculator tools, available on the product website, can be used to design a single output synchronous buck converter or an isolated dual output Fly-Buck converter using the LM5161. See application note Designing an Isolated Buck (Fly-Buck) Converter for a detailed design guide for the Fly-Buck converter. Alternatively, the online WEBENCH® Tool can be used to create a complete buck or Fly-Buck designs and generate the bill of materials, estimated efficiency, solution size, and cost of the complete solution.Typical Applications describes a few application circuits using the LM5161 with detailed, step-by-step design procedures.

Typical Applications

LM5161 Synchronous Buck (15-V to 95-V Input, 12-V Output, 1-A Load)

A typical application example is a synchronous buck converter operating from a wide input voltage range of 15 V to 95 V and providing a stable 12 V output voltage with maximum output current capability of 1 A. The complete schematic for a typical buck application circuit with LM5161 in diode emulation is shown in Figure 25 . In the application schematic below, the components are labeled by their respective component numbers instead of the descriptive name used in the previous sections. For example, R1 represents RON and so on.

LM5161 schematic_LM5161PWPBKEVM_snvu504.gif Figure 25. Synchronous Buck Application Circuit with LM5161

Design Requirements

A typical synchronous-buck application introduced in LM5161 Synchronous Buck (15-V to 95-V Input, 12-V Output, 1-A Load) , Table 3 summarizes the operating parameters:

Table 3. Design Parameters

Input voltage range 15-V to 80-V
output 12-V
Full load current 1-A
Nominal switching frequency 300 kHz
Light load operating mode CCM, FPWM=1
Jumper JP1 Pins 1-2 connected

Detailed Design Procedure

Custom Design With WEBENCH® Tools

Click here to create a custom design using the LM5161 device with the WEBENCH® Power Designer.

  1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
  2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
  3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

  • Run electrical simulations to see important waveforms and circuit performance
  • Run thermal simulations to understand board thermal performance
  • Export customized schematic and layout into popular CAD formats
  • Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at

Output Resistor Divider Selection

With the required output voltage set point at 12 V and VFB = 2 V (typical), the ratio of R8 (RFB1) to R7 (RFB2) can be calculated using Equation 6:

Equation 6. LM5161 eq06_snvsa03.gif

The resistor ratio calculates to be 5:1. Standard values of R8 (RFB1) = 2 kΩ and R7 (RFB2 ) =10 kΩ are chosen. Higher or lower resistor values could be used as long as the ratio of 5:1 is maintained.

Frequency Selection

The duty cycle required to maintain output regulation at the minimum input voltage restricts the maximum switching frequency of LM5161. The maximum value of the minimum forced OFF-time TOFF,min (max), limits the duty cycle and therefore the switching frequency. The maximum frequency that avoids output dropout at minimum input voltage can be calculated from Equation 7.

Equation 7. LM5161 eq07_snvsa03.gif

For this design example, the maximum frequency based on the minimum OFF-time limitation for TOFF,min(typ) = 170 ns is calculated to be FSW,max(@VIN,min) = 1.2 MHz. This value is above 1 MHz, the maximum possible operating frequency of the LM5161. Therefore, the minimum OFF-time parameter restricts the maximum achievable switching frequency calculation in this application.

At the maximum input voltage, the maximum switching frequency of LM5161 is restricted by the minimum ON-time, TON,min which limits the minimum duty cycle of the converter. The maximum frequency at maximum input voltage can be calculated using Equation 8.

Equation 8. LM5161 eq08_snvsa03.gif

Using Equation 8 and TON,min (typ) = 150 ns, the maximum achievable switching frequency is FSW,max(@VIN,min)= 1000 kHz. Taking this value as the maximum possible operational switching frequency over the input voltage range in this application, a nominal switching frequency of FSW = 300 kHz is chosen for this design.

The value of the resistor, RON sets the nominal switching frequency based on Equation 9.

Equation 9. LM5161 RON_VS_FSW_eq_R1_snvu504.gif

For this particular application with FSW = 300 kHz, RON calculates to be 396 kΩ . Selecting a standard value for R1 (RON) = 402 kΩ (±1%) results in a nominal frequency of 296 kHz. The resistor value may need to adjusted further in order to achieve the required switching frequency as the switching frequency in Constant ON-Time converters varies slightly(±10%) with input voltage and/or output current. Operation at a lower nominal switching frequency will result in higher efficiency but increase in the inductor and capacitor values leading to a larger total solution size.

Inductor Selection

The inductor is selected to limit the inductor ripple current to a value between 20 and 40 percent of the maximum load current. The minimum value of the inductor required in this application can be calculated from Equation 10:

Equation 10. LM5161 eq10_snvsa03.gif

Based on Equation 10 , the minimum value of the inductor is calculated to be 85 µH for VIN = 80-V (max) and inductor current ripple will be 40 percent of the maximum load current. Allowing some margin for inductance variation and inductor saturation, a higher standard value of L1 (L) = 100 µH is selected for this design.

The peak inductor current at maximum load must be smaller than the minimum current limit threshold of the high side FET as given in Electrical Characteristics table. The inductor current ripple at any input voltage is given by:

Equation 11. LM5161 eq11_snvsa03.gif

The peak-to-peak inductor current ripple is calculated to be 81 mA and 341 mA at the minimum and maximum input voltages respectively. The maximum peak inductor current in the buck FET is given by Equation 12:

Equation 12. LM5161 eq12_snvsa03.gif

In this design with maximum output current of 1-A, the maximum peak inductor current is calculated to be approximately 1.17 A at VIN,max = 80 V, which is less than the minimum high-side FET current limit threshold.

The saturation current of the inductor must also be carefully considered. The peak value of the inductor current will be bound by the high side FET current limit during overload or short circuit conditions. Based on the high side FET current limit specification in the Electrical Characteristics, an inductor with saturation current rating above 1.9 A (max) should be selected.

Output Capacitor Selection

The output capacitor is selected to limit the capacitive ripple at the output of the regulator. Maximum capacitive ripple is observed at maximum input voltage. The output capacitance required for a ripple voltage ∆VO across the capacitor is given by Equation 13.

Equation 13. LM5161 eq13_snvsa03.gif

Substituting ∆VO, ripple = 10 mV gives COUT = 15 μF. Two standard 10 μF ceramic capacitors in parallel (C11, C12) are selected. An X7R type capacitor with a voltage rating 25 V or higher should be used for COUT (C11, C12) to limit the reduction of capacitance due to dc bias voltage.

Series Ripple Resistor - RESR (FPWM = 1)

If the FPWM = 1, i.e. the FPWM pin is pulled high as when connected to VCC, a series resistor in series with the output capacitor or the external ripple injection circuit must be selected such that sufficient ripple injection (> 25mV) is ensured at the feedback pin FB. The ripple produced by RESR is proportional to the inductor current ripple, and therefore, RESR should be chosen for minimum inductor current ripple which occurs at minimum input voltage. The RESR is calculated by Equation 14.

Equation 14. LM5161 eq14_snvsa03.gif

With VO = 12 V, VREF = 2 V and ΔIL, min = 81 mA (at VIN, min= 15 V) as calculated in Equation 11, Equation 14 requires an RESR greater than or equal to 1.87 Ω. Selecting R4 (RESR) = 2 Ω results in approximately 700 mV of maximum output voltage ripple at VIN,max. However due to the internal DC Error correction loop, the load and line regulation will be much improved, despite the addition of a large RESR in the circuit. For applications which require even lower output voltage ripple, Type 2 or Type 3 ripple injection circuits must be used, as described in Ripple Configuration. In this design example, with the FPWM =1 (i.e. the FPWM pin is pulled up to VCC) a 0 Ω ESR resistor is selected and the external Type 3 ripple injection circuit is used.

VCC and Bootstrap Capacitor

The VCC capacitor charges the bootstrap capacitor during the OFF-time of the high-side switch and powers internal logic circuits and the low side sync FET gate driver. The bootstrap capacitor biases the high-side gate driver during the high-side FET ON-time. A good value for C13 (CVCC) is 1 µF. A good choice for C1 (CBST) is 10 nF. Both must be high quality X7R ceramic capacitors.

Input Capacitor Selection

The input capacitor must be large enough to limit the input voltage ripple to an acceptable level. Equation 15 provides the input capacitance CIN required for a worst case input ripple of ∆VIN, ripple.

Equation 15. LM5161 eq15_snvsa03.gif

CIN (C4, C6) supplies most of the switch current during the ON-time to limit the voltage ripple at the VIN pin. At maximum load current, when the buck switch turns on, the current into the VIN pin quickly increases to the valley current of the inductor ripple and then ramps up to the peak of the inductor ripple during the ON-time of the high-side FET. The average current during the ON-time is the output load current. For a worst-case calculation, CIN must supply this average load current during the maximum ON-time, without letting the voltage at VIN drop more than the desired input ripple. For this design, the input voltage drop is limited to 0.5 V and the value of CIN is calculated using Equation 15.

Based on Equation 15, the value of the input capacitor is calculated to be approximately 1.68 µF at D = 0.5. Taking into account the decrease in capacitance over an applied voltage, two standard value ceramic capacitors of 2.2 μF are selected for C4 and C6. The input capacitors should be rated for the maximum input voltage under all operating and transient conditions. A 100-V, X7R dielectric was selected for this design.

A third input capacitor C5 is needed in this design as a bypass path for the high frequency component of the input switching current. The value of C5 is 0.1 μF and this bypass capacitor must be placed directly across VIN and PGND (pin 3 and 2) near the IC. The CIN values and location are critical to reducing switching noise and transients.

Soft-Start Capacitor Selection

The capacitor at the SS pin determines the soft-start time, that is the time for the output voltage to reach its final steady state value. The capacitor value is determined from Equation 16:

Equation 16. LM5161 eq16_snvsa03.gif

With C9 (CSS) set at 22 nF and the Vss = 2 V, ISS = 10 µA, the TStartup should measure approximately 4 ms.

EN/UVLO Resistor Selection

The UVLO resistors R3 (RUV2) and R9 (RUV1) set the input undervoltage lockout threshold and hysteresis according to Equation 17 and Equation 18:

Equation 17. LM5161 eq17_snvsa03.gif


Equation 18. LM5161 eq18_snvsa03.gif

From the Electrical Characteristics, IUVLO(HYS) = 20 μA (typical). To design for VIN rising threshold (VIN, UVLO(rising)) at 15 V and EN/UVLO hysteresis of 1.5 V, Equation 17 and Equation 18 yield RUV1 = 6.81 kΩ and RUV2 = 75 kΩ . Selecting 1% standard value of R9 (RUV1) = 6.81 kΩ and R3 (RUV2) = 75 kΩ results in UVLO threshold (rising) and hysteresis of 14.9 V and 1.5 V respectively.

Application Curves

LM5161 LoadReg_extVcc_fpwm1_r1_SNVU504.gif Figure 26. Load Regulation
LM5161 EFF_12VOUT_fpwm1_ext_vs_intVcc_SNVU504.gif Figure 27. Efficiency vs IOUT (FPWM = 1)
LM5161 48V_FL_Startup_FPWM_1_SNVU540.png
Figure 28. EN/UVLO Start-up at VIN= 48 V and IOUT = 1 A
LM5161 48V_FL_EnToggle_FPWM_1_Revised_SNVU540.png Figure 30. EN/UVLO Start-up at VIN= 48 V and RLOAD = 12 Ω at FPWM = 1
LM5161 48V_0-1-0_FPWM_1_SNVU540.png Figure 32. Load Transient (0 A - 1 A) at VIN = 48 V
at FPWM = 1
LM5161 48VIN_NL_PreBiasENstartup_FPWM_1_Revised_SNVU540.png Figure 29. Pre-Bias (11.5 V) Start-up at VIN= 48 V at No Load & FPWM = 1
LM5161 48V_0-1-0_FPWM_0_Revised_SNVU540.png Figure 31. Load Transient (0 A - 1 A) at VIN = 48 V
at FPWM = 0
LM5161 48V_FL-SC-FL_SNVU540.png Figure 33. Output Short-Circuit at VIN = 48 V
(Full Load to Short)

LM5161 Isolated Fly-Buck (36-V to 72-V Input, 12-V, 12-W Isolated Output)

A typical application example for an isolated Fly-Buck converter operates over an input voltage range of 36 V to 72 V. It provides a stable 12 V isolated output voltage with output power capability of 10 W. The complete schematic of the Fly-Buck application circuit is shown in Figure 34.

LM5161 schematic_LM5161FBKEVM_snvu504.gif Figure 34. 12-V, 10-W Fly-Buck Schematic

LM5161 Fly-Buck Design Requirements

The LM5161 Fly-Buck application example is designed to operate from a nominal 48-V DC supply with line variations from 36-V to 72-V. This example provides a space-optimized and efficient 12-V isolated output solution with secondary load current capability from 0-A to 800 mA. The primary side remains unloaded in this application. The switching frequency is set at 300 kHz (nominal). This design achieves greater than 88% peak efficiency.

Table 4. Design Parameters

Input voltage range 36 V - 72 V
Isolated output 12 V (+/- 10%)
Isolated load current range (IISO) 0-A to 0.8-A
Nominal switching frequency 300 KHz
Peak efficiency ~87%
Operation mode FPWM = 1

Detailed Design Procedure

The Fly-Buck converter design procedure closely follows the buck converter design outlined in LM5161 Synchronous Buck (15-V to 95-V Input, 12-V Output, 1-A Load). The selection of primary output voltage, transformer turns ratio, rectifier diode, and output capacitors are covered here.

Selection of VOUT and Turns Ratio

The primary output voltage in a Fly-Buck converter should be no more than one half of the minimum input voltage. Therefore, at the minimum VIN of 36 V, the primary output voltage ( VOUT ) should be no higher than 18 V. The isolated output voltage of VOUTISO in Figure 34 is set at 12 V by selecting a transformer with a turns ratio (N1:N2 :: NPRI:NSEC) of 1:1. Using this turns ratio, the required primary output voltage VOUT is calculated in Equation 19:

Equation 19. LM5161 eq3_snvu505.gif

The 0.7 V (VFD1) added to VOUTISO in Equation 19 represents the forward voltage drop of the secondary rectifier diode. By setting the primary output voltage VOUT to 12.7-V by selecting the correct feedback resistors, the secondary voltage is regulated at 12-V nominally. Adjustment of the primary side VOUT may be required to compensate for voltage errors due to the leakage inductance of the transformer, the resistance of the transformer windings, the diode drop in the power path on the secondary side and the low-side FET of the LM5161.

Secondary Rectifier Diode

The secondary side rectifier diode must block the maximum input voltage reflected at secondary side switch node. The minimum diode reverse voltage V(RD1) rating is given in Equation 20:

Equation 20. LM5161 EQ20_REV2_snvu505.gif

A diode of 100-V or higher reverse voltage rating must be selected in this application. If the input voltage (VIN) has transients above the normal operating maximum input voltage of 72 V, then the worst-case transient input voltage must be used in the Equation 20 while selecting the secondary side rectifier diode.

External Ripple Circuit

The FPWM pin in the LM5161 should never be grounded or left open when used in a Fly-Buck application. Type 3 ripple circuit is required for Fly-Buck applications. Follow the design procedure used in the buck converter for selecting the Type 3 ripple injection components. See Ripple Configuration for ripple design information.

Output Capacitor (CVISO)

The Fly-Buck output capacitor conducts higher ripple current than a buck converter output capacitor. The ripple voltage across the isolated output capacitor is calculated based on the time the rectifier diode is off. During this time the entire output current is supplied by the output capacitor. The required capacitance for the worst-case ripple voltage can be calculated using Equation 21 where, ΔVISO is the expected ripple voltage at the secondary output.

Equation 21. LM5161 eq21_Rev1_snvsae3.gif

Equation 21 is an approximation and ignores the ripple components associated with ESR and ESL of the output capacitor. For a ΔVISO = 100 mV, Equation 21 requires CVISO = 11.12 µF. When selecting the CVISO output capacitors (C2 and C3 in the Figure 34), the DC bias must be considered in order to ensure sufficient capacitance over the output voltage.

Application Curves

LM5161 VReg_FBK_SNVU505.gif Figure 35. Load Regulation
LM5161 steadystate_48vin_0.5a_Rev1_snvu505.png Figure 37. Steady State at VIN = 48 V
and IOUT2 = 500 mA
LM5161 Startup_48vin_0.5a_Rev1_snvu505.png Figure 39. VIN Start-up at IISO = 500 mA
LM5161 Eff_FBK_SNVU505.gif Figure 36. Efficiency vs IISO
LM5161 48V_0.25-0.75_FBK_SNVSAE3.png Figure 38. Secondary Load Transient
at IISO = 250 mA - 750 mA
LM5161 nl_sc_48vin_Rev1_snvu505.png Figure 40. Secondary-Side Short at IOUT2 = 0 A
and IPRI = 0 A

Ripple Configuration

LM5161 uses a Constant-On-Time (COT) control scheme, in which the ON-time is terminated by a one-shot, and the OFF-time is terminated by the feedback voltage (VFB) falling below the reference voltage. Therefore, for stable operation, the feedback voltage must decrease monotonically and in phase with the inductor current during the OFF-time. Furthermore, this change in feedback voltage (VFB) during OFF-time must be large enough to dominate any noise present at the feedback node.

Table 5 presents three different methods for generating appropriate voltage ripple at the feedback node. Type 1 and Type 2 ripple circuits couple the ripple from the output of the converter to the feedback node (FB). The output voltage ripple has two components:

  1. Capacitive ripple caused by the inductor current ripple charging or discharging the output capacitor.
  2. Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor and R3.

The capacitive ripple is out-of-phase with the inductor current. As a result, the capacitive ripple does not decrease monotonically during the OFF-time. The resistive ripple is in phase with the inductor current and decreases monotonically during the OFF-time. The resistive ripple must exceed the capacitive ripple at output (VOUT) for stable operation. If this condition is not satisfied unstable switching behavior is observed in COT converters, with multiple ON-time bursts in close succession followed by a long OFF-time.

Type 3 ripple method uses a ripple injection circuit with RA, CA and the switch node (SW) voltage to generate a triangular ramp. This triangular ramp is then AC-coupled into the feedback node (FB) using the capacitor CB. Because this circuit does not use the output voltage ripple, it is suited for applications where low output voltage ripple is imperative. See application note Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT) Regulator Designs for more details for each ripple generation method.

Table 5. Ripple Configuration

Lowest Cost Reduced Ripple Minimum Ripple
LM5161 esr_ripple_snvsae3.gif
LM5161 reduced_rippleinj_snvsae3.gif
LM5161 ripple_inj_snvsae3.gif
Equation 22. LM5161 eq22_low_cost_snvsa03.gif
Equation 23. LM5161 eq23_reduce_ripple_snvsa03.gif
Equation 24. LM5161 eq24_snvsae3.gif

Do's and Don'ts

As mentioned earlier in Soft-Start , the SS capacitor CSS, must be more than 1 nF in both Buck and Fly-Buck applications. Apart from determining the start-up time, this capacitor serves for the external compensation of the internal GM error amplifier. A minimum value of 1 nF is necessary to maintain stability. The SS pin must not be left floating.

When the FPWM pin is shorted to ground or left unconnected, no external ripple injection is necessary in a Buck application. Should an external feedback ripple circuit be configured when FPWM = 0, it will produce higher ripple at the output.

Add a resistor (>3Ω) in series with the BST capacitor when using the part in FPWM = 0, as described in detail in Forced Pulse Width Modulation (FPWM) Mode.

When configured as a Fly-Buck, the FPWM pin must always be connected to VCC. A Fly-Buck application must operate in the continuous conduction mode all the time in order to maintain adequate voltage regulation on the secondary side. FPWM = 0 is not a valid mode in the Fly-Buck application.