10.1 Layout Guidelines
A proper layout is essential for optimum performance of the circuit. In particular, observe the following layout guidelines:
- CIN: The loop consisting of input capacitor (CIN), VIN pin, and PGND pin carries the switching current. Therefore, in the LM5161, the input capacitor must be placed close to the IC, directly across VIN and PGND pins, and the connections to these two pins should be direct to minimize the loop area. In general it is not possible to place all of input capacitances near the IC. However, a good layout practice includes placing the bulk capacitor as close as possible to the VIN pin (see Figure 41). When using the LM5161 HTSSOP-14 package, a bypass capacitor (Cbyp) measuring ~0.1 μF must be placed directly across VIN and PGND (pin 3 and 2), as close as possible to the IC while complying with all layout design rules.
- The RON resistor between the VIN and the RON pin and the SS capacitor should be placed as close as possible to their respective pins.
- CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high-side and low-side gate drivers. These two capacitors should also be placed as close to the IC as possible, and the connecting trace lengths and the loop area must be kept at minimum (see Figure 41).
- The feedback trace carries the output voltage information and a small ripple component that is necessary for proper operation of the LM5161. Therefore, care must be taken while routing the feedback trace to avoid coupling any noise into this pin. In particular, the feedback trace must be short and not run close to magnetic components, or parallel to any other switching trace.
- In FPWM=1 mode, if a ripple injection circuit is being used for ripple generation at the FB pin, it is considered a good layout practice to lay out the feedback ripple injection DC trace and the VOUT trace differentially. This scheme helps in reducing the scope for any noise injection at the FB pin.
- SW trace: The SW node switches rapidly between VIN and GND every cycle and is therefore a source of noise. The SW node area must be kept at minimum. In particular, the SW node should not be inadvertently connected to a copper plane or pour.