SNVSAE3B March   2016  – November 2017 LM5161


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Control Circuit
      2. 7.3.2  VCC Regulator
      3. 7.3.3  Regulation Comparator
      4. 7.3.4  Soft-Start
      5. 7.3.5  Error Transconductance (GM) Amplifier
      6. 7.3.6  On-Time Generator
      7. 7.3.7  Current Limit
      8. 7.3.8  N-Channel Buck Switch and Driver
      9. 7.3.9  Synchronous Rectifier
      10. 7.3.10 Enable / Undervoltage Lockout (EN/UVLO)
      11. 7.3.11 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Pulse Width Modulation (FPWM) Mode
      2. 7.4.2 Undervoltage Detector
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 LM5161 Synchronous Buck (15-V to 95-V Input, 12-V Output, 1-A Load)
        1. Design Requirements
        2. Detailed Design Procedure
          1.  Custom Design With WEBENCH® Tools
          2.  Output Resistor Divider Selection
          3.  Frequency Selection
          4.  Inductor Selection
          5.  Output Capacitor Selection
          6.  Series Ripple Resistor - RESR (FPWM = 1)
          7.  VCC and Bootstrap Capacitor
          8.  Input Capacitor Selection
          9.  Soft-Start Capacitor Selection
          10. EN/UVLO Resistor Selection
        3. Application Curves
      2. 8.2.2 LM5161 Isolated Fly-Buck (36-V to 72-V Input, 12-V, 12-W Isolated Output)
        1. LM5161 Fly-Buck Design Requirements
        2. Detailed Design Procedure
          1. Selection of VOUT and Turns Ratio
          2. Secondary Rectifier Diode
          3. External Ripple Circuit
          4. Output Capacitor (CVISO)
        3. Application Curves
      3. 8.2.3 Ripple Configuration
    3. 8.3 Do's and Don'ts
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Custom Design With WEBENCH® Tools
    2. 11.2 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Layout Guidelines

A proper layout is essential for optimum performance of the circuit. In particular, observe the following layout guidelines:

  • CIN: The loop consisting of input capacitor (CIN), VIN pin, and PGND pin carries the switching current. Therefore, in the LM5161, the input capacitor must be placed close to the IC, directly across VIN and PGND pins, and the connections to these two pins should be direct to minimize the loop area. In general it is not possible to place all of input capacitances near the IC. However, a good layout practice includes placing the bulk capacitor as close as possible to the VIN pin (see Figure 41). When using the LM5161 HTSSOP-14 package, a bypass capacitor (Cbyp) measuring ~0.1 μF must be placed directly across VIN and PGND (pin 3 and 2), as close as possible to the IC while complying with all layout design rules.
  • The RON resistor between the VIN and the RON pin and the SS capacitor should be placed as close as possible to their respective pins.
  • CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high-side and low-side gate drivers. These two capacitors should also be placed as close to the IC as possible, and the connecting trace lengths and the loop area must be kept at minimum (see Figure 41).
  • The feedback trace carries the output voltage information and a small ripple component that is necessary for proper operation of the LM5161. Therefore, care must be taken while routing the feedback trace to avoid coupling any noise into this pin. In particular, the feedback trace must be short and not run close to magnetic components, or parallel to any other switching trace.
  • In FPWM=1 mode, if a ripple injection circuit is being used for ripple generation at the FB pin, it is considered a good layout practice to lay out the feedback ripple injection DC trace and the VOUT trace differentially. This scheme helps in reducing the scope for any noise injection at the FB pin.
  • SW trace: The SW node switches rapidly between VIN and GND every cycle and is therefore a source of noise. The SW node area must be kept at minimum. In particular, the SW node should not be inadvertently connected to a copper plane or pour.

Layout Example

LM5161 layout_ex_snvsae3.gif Figure 41. Typical Buck Layout Example with the LM5161