SNVSC75 april   2023 LM5171-Q1

ADVANCE INFORMATION  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 7.3.2  Undervoltage Lockout (UVLO) and Controller Enable or Disable
      3. 7.3.3  High Voltage Inputs (HV1, HV2)
      4. 7.3.4  Current Sense Amplifier
      5. 7.3.5  Control Commands
        1. 7.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 7.3.5.2 Direction Command (DIR1 and DIR2)
        3. 7.3.5.3 Channel Current Setting Commands (ISET1 and ISET2)
      6. 7.3.6  Channel Current Monitor (IMON1, IMON2)
        1. 7.3.6.1 Individual Channel Current Monitor
        2. 7.3.6.2 Multiphase Total Current Monitoring
      7. 7.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 7.3.8  Inner Current Loop Error Amplifier
      9. 7.3.9  Outer Voltage Loop Error Amplifier
      10. 7.3.10 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 7.3.10.1 Soft-Start Control by the SS/DEM Pins
        2. 7.3.10.2 DEM Programming
        3. 7.3.10.3 FPWM Programming and Dynamic FPWM and DEM Change
        4. 7.3.10.4 SS Pin as the Restart Timer
      11. 7.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      12. 7.3.12 Emergent Latched Shutdown (DT/SD)
      13. 7.3.13 PWM Comparator
      14. 7.3.14 Oscillator (OSC)
      15. 7.3.15 Synchronization to an External Clock (SYNCI, SYNCO)
      16. 7.3.16 Overvoltage Protection (OVP)
      17. 7.3.17 Multiphase Configurations (SYNCO, OPT)
        1. 7.3.17.1 Multiphase in Star Configuration
        2. 7.3.17.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 7.3.17.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      18. 7.3.18 Thermal Shutdown
    4. 7.4 Programming
      1. 7.4.1 Dynamic Dead Time Adjustment
      2. 7.4.2 UVLO Programming
    5. 7.5 I2C Serial Interface
      1. 7.5.1 REGFIELD Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Small Signal Model
        1. 8.1.1.1 Current Loop Small Signal Model
        2. 8.1.1.2 Current Loop Compensation
        3. 8.1.1.3 Voltage Loop Small Signal Model
        4. 8.1.1.4 Voltage Loop Compensation
    2. 8.2 Typical Application
      1. 8.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Determining the Duty Cycle
          2. 8.2.1.2.2  Oscillator Programming
          3. 8.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 8.2.1.2.4  Current Sense (RCS)
          5. 8.2.1.2.5  Current Setting Limits (ISETx)
          6. 8.2.1.2.6  Peak Current Limit
          7. 8.2.1.2.7  Power MOSFETS
          8. 8.2.1.2.8  Bias Supply
          9. 8.2.1.2.9  Boot Strap
          10. 8.2.1.2.10 OVP
          11. 8.2.1.2.11 Dead Time
          12. 8.2.1.2.12 Channel Current Monitor (IMONx)
          13. 8.2.1.2.13 UVLO Pin Usage
          14. 8.2.1.2.14 HVx Pin Configuration
          15. 8.2.1.2.15 Loop Compensation
          16. 8.2.1.2.16 Soft Start
          17. 8.2.1.2.17 PWM to ISET Pins
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 High Voltage Inputs (HV1, HV2)

Figure 7-2 shows the external and internal configuration for the HV1 and HV2 pins. Both pins are rated at 85 Vdc. For independent channel operation, the HV1 and HV2 must be directly connected to the HV-port voltage rails for each channel, respectively, which are not necessarily the same HV-port. When operating in parallel dual phase configuration to support high power, the two HV pins can be tied together and connect to the same HV-port. As shown in Figure 7-2, a small RC filter like 10 Ω and 0.1 µF can be applied at these two pins to bypass high frequency noises.

GUID-20230329-SS0I-BNKX-HMD3-XNQDL3TH3MGS-low.svg Figure 7-2 HV1 and HV2 Pins Configuration