SNVSC75 april   2023 LM5171-Q1

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 7.3.2  Undervoltage Lockout (UVLO) and Controller Enable or Disable
      3. 7.3.3  High Voltage Inputs (HV1, HV2)
      4. 7.3.4  Current Sense Amplifier
      5. 7.3.5  Control Commands
        1. 7.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 7.3.5.2 Direction Command (DIR1 and DIR2)
        3. 7.3.5.3 Channel Current Setting Commands (ISET1 and ISET2)
      6. 7.3.6  Channel Current Monitor (IMON1, IMON2)
        1. 7.3.6.1 Individual Channel Current Monitor
        2. 7.3.6.2 Multiphase Total Current Monitoring
      7. 7.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 7.3.8  Inner Current Loop Error Amplifier
      9. 7.3.9  Outer Voltage Loop Error Amplifier
      10. 7.3.10 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 7.3.10.1 Soft-Start Control by the SS/DEM Pins
        2. 7.3.10.2 DEM Programming
        3. 7.3.10.3 FPWM Programming and Dynamic FPWM and DEM Change
        4. 7.3.10.4 SS Pin as the Restart Timer
      11. 7.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      12. 7.3.12 Emergent Latched Shutdown (DT/SD)
      13. 7.3.13 PWM Comparator
      14. 7.3.14 Oscillator (OSC)
      15. 7.3.15 Synchronization to an External Clock (SYNCI, SYNCO)
      16. 7.3.16 Overvoltage Protection (OVP)
      17. 7.3.17 Multiphase Configurations (SYNCO, OPT)
        1. 7.3.17.1 Multiphase in Star Configuration
        2. 7.3.17.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 7.3.17.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      18. 7.3.18 Thermal Shutdown
    4. 7.4 Programming
      1. 7.4.1 Dynamic Dead Time Adjustment
      2. 7.4.2 UVLO Programming
    5. 7.5 I2C Serial Interface
      1. 7.5.1 REGFIELD Registers
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Small Signal Model
        1. 8.1.1.1 Current Loop Small Signal Model
        2. 8.1.1.2 Current Loop Compensation
        3. 8.1.1.3 Voltage Loop Small Signal Model
        4. 8.1.1.4 Voltage Loop Compensation
    2. 8.2 Typical Application
      1. 8.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Determining the Duty Cycle
          2. 8.2.1.2.2  Oscillator Programming
          3. 8.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 8.2.1.2.4  Current Sense (RCS)
          5. 8.2.1.2.5  Current Setting Limits (ISETx)
          6. 8.2.1.2.6  Peak Current Limit
          7. 8.2.1.2.7  Power MOSFETS
          8. 8.2.1.2.8  Bias Supply
          9. 8.2.1.2.9  Boot Strap
          10. 8.2.1.2.10 OVP
          11. 8.2.1.2.11 Dead Time
          12. 8.2.1.2.12 Channel Current Monitor (IMONx)
          13. 8.2.1.2.13 UVLO Pin Usage
          14. 8.2.1.2.14 HVx Pin Configuration
          15. 8.2.1.2.15 Loop Compensation
          16. 8.2.1.2.16 Soft Start
          17. 8.2.1.2.17 PWM to ISET Pins
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  9. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Current Loop Small Signal Model

Figure 8-1 shows the current loop block diagram of each phase in buck mode. VHV is the input while VLV is the output.

GUID-20230302-SS0I-XZFL-GJ1R-5CTN63PVBSV6-low.svg Figure 8-1 Buck Loop Block Diagram

The inner current loop should be designed first. The average current-mode control loop of buck mode can be modeled as:Figure 8-2

GUID-20230316-SS0I-DMKF-NQHX-PNN0SP85TKX2-low.svg Figure 8-2 Current Loop Block Diagram

The buck power plant transfer function from the duty cycle (d) to the channel inductor current (iLm) is determined by the following:

Equation 23. Gid_BKs=i^Lmd^=VHVROUT_BK×1+sωZ_il_BK1+sω0_BK×QBK+s2ω0_BK2

where

Equation 24. R O U T _ B K = V L V I L m a x
Equation 25. ω Z _ i l _ B K = 1 R O U T _ B K × C O U T _ B K
Equation 26. ω0_BK=1Lm×COUT_BK
Equation 27. QBK=1ω0_BK×1LmROUT_BK+RESR_BK+RCS+RS×COUT_BK
  • Lm is the power inductor,
  • RCS is the current sense resistor,
  • RS is the equivalent total resistance along the current path excluding RCS,
  • COUT_BK is the output capacitance for each phase in buck mode. For a system with np phases, COUT_BK is 1/np times the total capacitance.
  • RESR_BK is the output capacitor equivalent series resistance (ESR) for each phase in buck mode. For np phase system, RESR_BK is np times total system output capacitor ESR.

Figure 8-3 shows the current loop block diagram in boost mode. VLV is the input while VHV is the output.

GUID-20230302-SS0I-HZ85-NK0T-2JFT5SXLBK5G-low.svg Figure 8-3 Boost Loop Block Diagram

The average current-mode control loop of boost mode is the same as buck as shown in Figure 8-2. But the transfer function of the boost power stage Gid(s) and Gvd(s) is different from that of buck power stage.

The boost power plant transfer function from the duty cycle (d) to the channel inductor current (iLm) is determined by the following:

Equation 28. Gid_BSTs=i^Lmd^=2×VLV1-D3×ROUT_BST×1+sωZ_il_BST1+sω0_BST×QBST+s2ω0_BST2

where

Equation 29. D = 1 - V L V V H V
Equation 30. R O U T _ B S T = V H V 2 V L V × I L m a x
Equation 31. ω Z _ i l _ B S T = 2 R O U T _ B S T × C O U T _ B S T
Equation 32. ω0_BST=1-DLm×COUT_BST
Equation 33. QBST=1-Dω0_BST×1Lm1-D×ROUT_BST+RCS+RS×COUT_BST1-D+RESR_BST×COUT_BST
  • COUT_BST is the output capacitance for each phase in boost mode. For a system with np phases , COUT_BST is 1/np times the total capacitance.
  • RESR_BST is the output capacitor equivalent series resistance (ESR) for each phase in boost mode. For a system with np phases, RESR_BST is np times total system output capacitor ESR.

When we select the current loop cross over frequency at 1/6 of switching frequency, Gid_BK(s) can be simplified. For the numerator, s×ROUT_BK×COUT_BK dominates. And for the denominator, s20_BK2 dominates. Equation 23 can be simplified as:

Equation 34. Gid_BKs=VHVROUT_BK×1+sωZ_il_BKs2ω0_BK2=VHVs×Lm

Similarly, Equation 28 can be simplified as:

Equation 35. Gid_BSTs=2×VLV1-D3×ROUT_BST×sωZ_il_BSTs2ω0_BST2=VHVs×Lm

It can be observed that the same duty cycle (d) to channel inductor current (iLm) transfer function is shared by both buck and boost mode:

Equation 36. Gids=VHVs×Lm

So compensator for buck current loop and boost current loop can also be shared.