SLVSKK8 August   2026 LM7311

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO and UVP)
      2. 7.3.2 Overvoltage Lockout (OVLO)
      3. 7.3.3 Inrush Current, Overcurrent, and Short Circuit Protection
        1. 7.3.3.1 Slew Rate (dVdt) and Inrush Current Control
        2. 7.3.3.2 Short-Circuit Protection
        3. 7.3.3.3 Current Limit in Start-up
      4. 7.3.4 Analog Load Current Monitor
      5. 7.3.5 Reverse Current Protection
      6. 7.3.6 Overtemperature Protection (OTP)
      7. 7.3.7 Fault Response and Indication (FLT)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Single Device, Self-Controlled
    3. 8.3 Typical Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
        1. 8.3.2.1 Setting Undervoltage Threshold
        2. 8.3.2.2 Setting Output Voltage Rise Time (tR)
        3. 8.3.2.3 Setting Analog Current Monitor Voltage (IMON) Range
        4. 8.3.2.4 39
      3. 8.3.3 Application Curves
    4. 8.4 Active ORing
    5. 8.5 Power Supply Recommendations
      1. 8.5.1 Transient Protection
      2. 8.5.2 Output Short-Circuit Measurements
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Reference
    2. 11.2 Package Option Addendum
    3. 11.3 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.1 Layout Guidelines

  • For all applications, a ceramic decoupling capacitor of 0.1 μF or greater is recommended between the IN terminal and GND terminal.
  • The desired placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the GND terminal of the IC.
  • High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current.
  • The GND terminal must be tied to the PCB ground plane at the terminal of the IC with the shortest possible trace. The PCB ground must be a copper plane or island on the board. TI recommends to have a separate ground plane island for the eFuse. This plane does not carry any high currents and serves as a quiet ground reference for all the critical analog signals of the eFuse. The device ground plane must be connected to the system power ground plane using a star connection.
  • The IN and OUT pads are used for heat dissipation. Connect to as much copper area on top and bottom PCB layers using as possible with thermal vias. The vias under the device also help to minimize the voltage gradient across the IN and OUT pads and distribute current uniformly through the device, which is essential to achieve the best on-resistance and current sense accuracy.
  • Locate the following support components close to the connection pins:
    • CdVdT
    • Resistors for the EN/UVLO pin
  • Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for CdVdt component to the device must be as short as possible to reduce parasitic effects on the soft start timing. These traces must not have any coupling to switching signals on the board.
  • Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device the diodes+ are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, a protection Schottky diode is recommended to address negative transients due to switching of inductive loads. TI also recommends to add a ceramic decoupling capacitor of 1 μF or greater between OUT and GND. These components must be physically close to the OUT pins. Care must be taken to minimize the loop area formed by the Schottky diode/bypass-capacitor connection, the OUT pin and the GND terminal of the IC.