The following operation description of the LM76002-Q1/LM76003-Q1 refers to the Functional Block Diagram and to the waveforms in Figure 10. The LM76002-Q1/LM76003-Q1 supplies a regulated output voltage by turning on the internal high side (HS) and low side (LS) NMOS switches with varying duty cycle (D). During high-side switch on-time tON, the SW pin voltage VSW swings up to approximately VIN, and the inductor current iL increase with linear slope. The HS switch is off by the control logic. During the HS switch off-time, tOFF, the LS switch is turned on. Inductor current discharges through the LS switch, which forces the VSW to swing below ground by the voltage drop across the LS switch. The regulator loop adjusts the duty cycle to maintain a constant output voltage. The control parameter of buck converter is defined as duty cycle D = tON / tSW. In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN.
The LM76002-Q1/LM76003-Q1 synchronous buck converter employs peak current-mode control topology. A voltage-feedback loop is used to get accurate DC-voltage regulation by adjusting the peak current command based on voltage offset. The peak inductor current is sensed from the HS switch and compared to the peak current to control the on-time of the HS switch. The voltage feedback loop is internally compensated, which allows command for fewer external components, makes it easy to design, and provides stable operation with almost any combination of output capacitors. The regulator operates with fixed switching frequency in continuous conduction mode (CCM) and discontinuous conduction mode (DCM). At very light load, the LM76002-Q1/LM76003-Q1 operates in PFM to maintain high efficiency, and the switching frequency decreases with reduced load current.