Minimize area of switched current loops. From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PC board layout as shown in the figure above. The high current loops that do not overlap have high di/dt content that causes observable high frequency noise on the output pin if the input capacitor CIN is placed at a distance away from the LM76002/LM76003. Therefore, place CIN as close as possible to the LM76002/LM76003 PVIN and PGND pins. This minimizes the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor must consist of a localized top-side plane that connects to the PGND pin.
Have a single point ground. The ground connections for the feedback, soft-start, and enable components should be routed to the AGND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior.
Minimize trace length to the FB pin net. Place both feedback resistors, RFBT and RFBB, close to the FB pin. Because the FB node is high impedance, maintain the copper area as small as possible. Route the traces from RFBT, RFBB away from the body of the LM76002/LM76003 to minimize possible noise pickup. Place Cff directly in parallel with RFBT.
Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so corrects for voltage drops and provide optimum output accuracy.
Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be connected to inner layer heat-spreading ground planes. For best results use a 10 × 10 via array (or greater) with a minimum via diameter of 12 mil thermal vias spaced 46.8 mil apart. Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125°C.