SNOS469J April   2000  – January 2015 LM8261


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics 2.7 V
    6. 6.6 Electrical Characteristics 5 V
    7. 6.7 Electrical Characteristics ±15 V
    8. 6.8 Typical Characteristics
  7. Application and Implementation
    1. 7.1 Block Diagram and Operational Description
      1. 7.1.1  A) Input Stage
      2. 7.1.2 B) Output Stage
    2. 7.2 Driving Capacitive Loads
    3. 7.3 Estimating the Output Voltage Swing
    4. 7.4 TFT Applications
    5. 7.5 Output Short Circuit Current and Dissipation Issues
    6. 7.6 Other Application Hints
      1. 7.6.1 LM8261 Advantages
  8. Power Supply Recommendations
  9. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Trademarks
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Layout

9.1 Layout Guidelines

Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and possible circuit oscillations. Texas Instruments suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization. See Table 2 for details. The LM8261 evaluation board(s) is a good example of high frequency layout techniques as a reference. General high-speed, signal-path layout suggestions include:

  • Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs. However, open up both ground and power planes around the capacitive sensitive input and output device pins as shown in Figure 58. After the signal is sent into a resistor, parasitic capacitance becomes more of a bandlimiting issue and less of a stability issue.
  • Use good, high-frequency decoupling capacitors (0.1 μF) on the ground plane at the device power pins as shown in Figure 58. Higher value capacitors (2.2 μF) are required, but may be placed further from the device power pins and shared among devices. For best high-frequency decoupling, consider X2Y supply-decoupling capacitors that offer a much higher self-resonance frequency over standard capacitors.
  • When using differential signal routing over any appreciable distance, use microstrip layout techniques with matched impedance traces.
  • The input summing junction is very sensitive to parasitic capacitance. Connect any Rf, and Rg elements into the summing junction with minimal trace length to the device pin side of the resistor, as shown in Figure 59. The other side of these elements can have more trace length if needed to the source or to ground.

9.2 Layout Example

LMH730316_callouts_layer1_v2.pngFigure 58. LM8261 Evaluation Board Layer 1
EVM_board_figure2_version4.pngFigure 59. LM8261 Evaluation Board Layer 2

Table 2. Evaluation Board Comparison

LM8261M5 SOT-23 LMH730216