SNOS725E May   1999  – March 2025 LMC6462 , LMC6464

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for LMC6462
    5. 5.5 Thermal Information for LMC6464
    6. 5.6 Electrical Characteristics for VS = ±2.25V or VS = 5V
    7. 5.7 Electrical Characteristics for VS = ±1.5V or VS = 3V
  7. 6 Typical Characteristics
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input Common-Mode Voltage Range
      2. 7.1.2 Rail-to-Rail Output
      3. 7.1.3 Capacitive Load Tolerance
      4. 7.1.4 Compensating for Input Capacitance
      5. 7.1.5 Offset Voltage Adjustment
      6. 7.1.6 Instrumentation Circuits
    2. 7.2 Typical Applications
      1. 7.2.1 Transducer Interface Circuits
      2. 7.2.2 LMC646x as a Comparator
      3. 7.2.3 Half-Wave and Full-Wave Rectifiers
      4. 7.2.4 Precision Current Source
      5. 7.2.5 Oscillators
      6. 7.2.6 Low Frequency Null
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
        1. 7.3.1.1 PCB Layout for High-Impedance Work
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
    2. 8.2 Documentation Support
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4 Thermal Information for LMC6462

THERMAL METRIC(1) LMC6462 UNIT
D (SOIC) P (PDIP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance  193 115 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 52.0 53.7 °C/W
RθJB Junction-to-board thermal resistance 56.9 39.5 °C/W
ψJT Junction-to-top characterization parameter 6.8 19.5 °C/W
ψJB Junction-to-board characterization parameter 56.1 38.5 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.