SNOS674G November   1997  – April 2020 LMC6482

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Rail-to-Rail Input
      2.      Rail-to-Rail Output
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics for V+ = 5 V
    6. 6.6 Electrical Characteristics for V+ = 3 V
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Amplifier Topology
      2. 7.3.2 Input Common-Mode Voltage Range
      3. 7.3.3 Rail-to-Rail Output
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Upgrading Applications
      2. 8.1.2 Data Acquisition Systems
      3. 8.1.3 Instrumentation Circuits
      4. 8.1.4 Spice Macromodel
    2. 8.2 Typical Applications
      1. 8.2.1 3-V Single-Supply Buffer Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Capacitive Load Compensation
          2. 8.2.1.2.2 Capacitive Load Tolerance
          3. 8.2.1.2.3 Compensating For Input Capacitance
          4. 8.2.1.2.4 Offset Voltage Adjustment
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Single-Supply Applications
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics for V+ = 5 V

unless otherwise specified, all limits specified for TJ = 25°C, V+ = 5 V, V = 0 V, VCM = VO = V+/2 and RL > 1 MΩ.
PARAMETER TEST CONDITIONS TJ = 25°C AT TEMPERATURE EXTREMES(6) UNIT
MIN TYP(1)   MAX(2)   MIN TYP(1)   MAX(2)  
DC ELECTRICAL CHARACTERISTICS
VOS Input offset voltage LMC6482AI 0.11 0.75 1.35 mV
LMC6482I 0.11 3 3.7
LMC6482M 0.11 3 3.8
TCVOS Input offset voltage average drift 1 μV/°C
IB Input current LMC6482AI 0.02 4 pA
LMC6482I 0.02 4
LMC6482M 0.02 10
IOS Input offset current LMC6482AI 0.01 2 pA
LMC6482I 0.01 2
LMC6482M 0.01 5
CIN Common-mode input capacitance 3 pF
RIN Input resistance 10 TeraΩ
CMRR Common-mode rejection ratio 0 V ≤ VCM ≤ 15 V
V+ = 15 V
LMC6482AI 70 82 67 dB
LMC6482I 65 82 62
LMC6482M 65 82 60
0 V ≤ VCM ≤ 5 V
V+ = 5 V
LMC6482AI 70 82 67
LMC6482I 65 82 62
LMC6482M 65 82 60
+PSRR Positive power supply rejection ratio 5 V ≤ V+ ≤ 15 V,
V = 0 V
VO = 2.5 V
LMC6482AI 70 82 67 dB
LMC6482I 65 82 62
LMC6482M 65 82 60
−PSRR Negative power supply rejection ratio −5 V ≤ V ≤ −15 V, V+ = 0 V
VO = −2.5 V
LMC6482AI 70 82 67 dB
LMC6482I 65 82 62
LMC6482M 65 82 60
VCM Input common-mode voltage V+ = 5 V and 15 V
For CMRR ≥ 50 dB
LMC6482AI V − 0.3 −0.25 0 V
LMC6482I V − 0.3 −0.25 0
LMC6482M V − 0.3 −0.25 0
LMC6482AI V+ + 0.25 V+ + 0.3 V+ V
LMC6482I V+ + 0.25 V+ + 0.3 V+
LMC6482M V+ + 0.25 V+ + 0.3 V+
AV Large signal voltage gain RL = 2 kΩ(3) Sourcing LMC6482AI 140 666 84 V/mV
LMC6482I 120 666 72
LMC6482M 120 666 60
Sinking LMC6482AI 35 75 20 V/mV
LMC6482I 35 75 20
LMC6482M 35 75 18
RL = 600 Ω(3) Sourcing LMC6482AI 80 300 48 V/mV
LMC6482I 50 300 30
LMC6482M 50 300 25
Sinking LMC6482AI 20 35 13 V/mV
LMC6482I 15 35 10
LMC6482M 15 35 8
VO Output swing V+ = 5 V
RL = 2 kΩ to V+/2
LMC6482AI 4.8 4.9 4.7 V
LMC6482I 4.8 4.9 4.7
LMC6482M 4.8 4.9 4.7
LMC6482AI 0.1 0.18 0.24
LMC6482I 0.1 0.18 0.24
LMC6482M 0.1 0.18 0.24
V+ = 5 V
RL = 600 Ω to V+/2
LMC6482AI 4.5 4.7 4.24 V
LMC6482I 4.5 4.7 4.24
LMC6482M 4.5 4.7 4.24
LMC6482AI 0.3 0.5 0.65
LMC6482I 0.3 0.5 0.65
LMC6482M 0.3 0.5 0.65
V+ = 15 V
RL = 2k Ω to V+/2
LMC6482AI 14.4 14.7 14.2 V
LMC6482I 14.4 14.7 14.2
LMC6482M 14.4 14.7 14.2
LMC6482AI 0.16 0.32 0.45
LMC6482I 0.16 0.32 0.45
LMC6482M 0.16 0.32 0.45
V+ = 15 V
RL = 600 Ω to V+/2
LMC6482AI 13.4 14.1 13 V
LMC6482I 13.4 14.1 13
LMC6482M 13.4 14.1 13
LMC6482AI 0.5 1 1.3
LMC6482I 0.5 1 1.3
LMC6482M 0.5 1 1.3
ISC Output short circuit current
V+ = 5 V
Sourcing, VO = 0 V LMC6482AI 16 20 12 mA
LMC6482I 16 20 12
LMC6482M 16 20 10
Sinking, VO = 5 V LMC6482AI 11 15 9.5 mA
LMC6482I 11 15 9.5
LMC6482M 11 15 8
ISC Output short circuit current
V+ = 15 V
Sourcing, VO = 0 V LMC6482AI 28 30 22 mA
LMC6482I 28 30 22
LMC6482M 28 30 20
Sinking,
VO = 12 V(5)
LMC6482AI 30 30 24 mA
LMC6482I 30 30 24
LMC6482M 30 30 22
IS Supply current Both Amplifiers
V+ = +5 V,
VO = V+/2
LMC6482AI 1 1.4 1.8 mA
LMC6482I 1 1.4 1.8
LMC6482M 1 1.4 1.9
Both Amplifiers
V+ = 15 V,
VO = V+/2
LMC6482AI 1.3 1.6 1.9 mA
LMC6482I 1.3 1.6 1.9
LMC6482M 1.3 1.6 2
AC ELECTRICAL CHARACTERISTICS
SR Slew rate(5) LMC6482AI 1 1.3 0.7 V/μs
LMC6482I 0.9 1.3 0.63
LMC6482M 0.9 1.3 0.54
GBW Gain-bandwidth product V+ = 15 V 1.5 MHz
φm Phase margin 50 Deg
Gm Gain margin 15 dB
Amp-to-amp isolation See  (4) 150 dB
en Input-referred voltage noise F = 1 kHz
Vcm = 1 V
37 nV/√Hz
In Input-referred current noise F = 1 kHz 0.03 pA/√Hz
T.H.D. Total harmonic distortion F = 10 kHz, AV = −2
RL = 10 kΩ,
VO = 4.1 VPP
0.01%
F = 10 kHz, AV = −2
RL = 10 kΩ,
VO = 8.5 VPP
V+ = 10 V
0.01%
Typical values represent the most likely parametric norm.
All limits are specified by testing or statistical analysis.
V+ = 15 V, VCM = 7.5 V and RL connected to 7.5 V. For sourcing tests, 7.5 V ≤ VO ≤ 11.5 V. For sinking tests, 3.5 V ≤ VO ≤ 7.5 V.
Input referred, V+ = 15 V and RL = 100 kΩ connected to 7.5 V. Each amp excited in turn with 1 kHz to produce VO = 12 VPP.
V + = 15V. Connected as voltage follower with 10-V step input. Number specified is the slower of either the positive or negative slew rates.
See Recommended Operating Conditions for operating temperature ranges.