SNOSDE2A October   2022  – December 2022 LMG2610

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 GaN Power FET Switching Parameters
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  GaN Power FET Switching Capability
      2. 8.3.2  Turn-On Slew-Rate Control
      3. 8.3.3  Current-Sense Emulation
      4. 8.3.4  Bootstrap Diode Function
      5. 8.3.5  Input Control Pins (EN, INL, INH)
      6. 8.3.6  INL - INH Interlock
      7. 8.3.7  AUX Supply Pin
        1. 8.3.7.1 AUX Power-On Reset
        2. 8.3.7.2 AUX Under-Voltage Lockout (UVLO)
      8. 8.3.8  BST Supply Pin
        1. 8.3.8.1 BST Power-On Reset
        2. 8.3.8.2 BST Under-Voltage Lockout (UVLO)
      9. 8.3.9  Over-Current Protection
      10. 8.3.10 Over-Temperature Protection
      11. 8.3.11 Fault Reporting
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Turn-On Slew-Rate Design
        2. 9.2.2.2 Current-Sense Design
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Solder-Joint Stress Relief
        2. 9.4.1.2 Signal-Ground Connection
        3. 9.4.1.3 CS Pin Signal
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • RRG|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.5 Input Control Pins (EN, INL, INH)

The EN pin is used to toggle the device between the active and standby modes described in Device Functional Modes.

The INL pin is used to turn the low-side GaN power FET on and off.

The INH pin is used to turn the high-side GaN power FET on and off.

The input control pins have a typical 1-V input-voltage-threshold hysteresis for noise immunity. The pins also have a typical 400 kΩ pull-down resistance to protect against floating inputs. The 400 kΩ saturates for typical input voltages above 4 V to limit the maximum input pull-down current to a typical 10 uA.

The INL turn-on action is impacted by the following conditions 1) Standby Mode, 2) AUX UVLO, 3) INH in control of Interlock, 4) Low-Side Over-Current Protection, and 5) Over-Temperature Protection.

The INH turn-on action is impacted by the following conditions 1) Standby Mode, 2) AUX UVLO, 3) INL in control of Interlock, 4) High-Side Over-Current Protection, and 5) Over-Temperature Protection.

The Standby Mode, AUX UVLO, and Over-Temperature Protection are the universal INL / INH blocking conditions. These conditions hold both GaN half-bridge power FETs off independent of INL and INH. Figure 8-3 shows the Universal Blocking Condition Operation. Note that the high-side FET does not turn on at transistion #4. INH only turns on the high-side FET if there is no universal blocking condition when INH goes to logic high. This avoids an incomplete high-side FET turn-on period which can create undesired spike voltages in the converter.



Figure 8-3 Universal INL / INH Blocking Condition Operation