SNOSCY4E March 2015 – October 2018 LMG5200
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY CURRENTS | ||||||
ICC | VCC Quiescent Current | LI = HI = 0V, VCC = 5V, HB-HS = 4.6V | 0.08 | 0.125 | mA | |
ICCO | Total VCC Operating Current | f = 500 kHz | 3.0 | 5.0 | mA | |
IHB | HB Quiescent Current | LI = HI = 0V, VCC = 5V, HB-HS = 4.6V | 0.09 | 0.150 | mA | |
IHBO | HB Operating Current | f = 500 kHz, 50% Duty cycle, VDD = 5V | 1.5 | 2.5 | mA | |
INPUT PINS | ||||||
VIH | High-Level Input Voltage Threshold | Rising Edge | 1.87 | 2.06 | 2.22 | V |
VIL | Low-Level Input Voltage Threshold | Falling Edge | 1.48 | 1.66 | 1.76 | V |
VHYS | Hysteresis between rising and falling threshold | 400 | mV | |||
RI | Input pull down resistance | 100 | 200 | 300 | kΩ | |
UNDER VOLTAGE PROTECTION | ||||||
VCCR | VCC Rising edge threshold | Rising | 3.2 | 3.8 | 4.5 | V |
VCC(hyst) | VCC UVLO threshold hysteresis | 200 | mV | |||
VHBR | HB Rising edge threshold | Rising | 2.5 | 3.2 | 3.9 | V |
VHB(hyst) | HB UVLO threshold hysteresis | 200 | mV | |||
BOOTSTRAP DIODE | ||||||
VDL | Low-Current forward voltage | IVDD-HB = 100µA | 0.45 | 0.65 | V | |
VDH | High current forward voltage | IVDD-HB = 100mA | 0.9 | 1.0 | V | |
RD | Dynamic Resistance | IVDD-HB = 100mA | 1.85 | 2.8 | Ω | |
HB-HS Clamp | Regulation Voltage | 4.65 | 5 | 5.2 | V | |
tBS | Bootstrap diode reverse recovery time | IF = 100 mA, IR = 100 mA | 40 | ns | ||
QRR | Bootstrap diode reverse recovery charge | VVIN = 50 V | 2 | nC | ||
POWER STAGE | ||||||
RDS(ON)HS | High-side GaN FET on-resistance | LI=0V, HI=VCC=5V, HB-HS=5V, VIN-SW=10A, TJ = 25℃ | 15 | 20 | mΩ | |
RDS(ON)LS | Low-side GaN FET on-resistance | LI=VCC=5V, HI=0V, HB-HS=5V, SW-PGND=10A, TJ = 25℃ | 15 | 20 | mΩ | |
VSD | GaN 3rd quadrant conduction drop | ISD = 500 mA, VIN floating, VVCC = 5 V, HI = LI = 0V | 2 | V | ||
IL-VIN-SW | Leakage from VIN to SW when the high-side GaN FET and low-side GaN FET are off | VIN = 80V, HI = LI = 0V, VVCC = 5V, TJ=25℃ | 25 | 150 | µA | |
IL-SW-GND | Leakage from SW to GND when the high-side GaN FET and low-side GaN FET are off | SW = 80V, HI = LI = 0V, VVCC = 5V, TJ=25℃ | 25 | 150 | µA | |
COSS | Output Capacitance of high-side GaN FET and low-side GaN FET | VDS=40V, VGS= 0V (HI = LI = 0V) | 266 | pF | ||
QG | Total Gate Charge | VDS=40V, ID= 10A, VGS= 5V | 3.8 | nC | ||
QOSS | Output Charge | VDS=40V, ID= 10A | 21 | nC | ||
QRR | Source to Drain Reverse Recovery Charge | Not including internal driver bootstrap diode | 0 | nC | ||
tHIPLH | Propagation delay: HI Rising(2) | LI=0V, VCC=5V, HB-HS=5V, VIN=30V | 29.5 | 50 | ns | |
tHIPHL | Propagation delay: HI Falling(2) | LI=0V, VCC=5V, HB-HS=5V, VIN=30V | 29.5 | 50 | ns | |
tLPLH | Propagation delay: LI Rising(2) | HI=0V, VCC=5V, HB-HS=5V, VIN=30V | 29.5 | 50 | ns | |
tLPHL | Propagation delay: LI Falling(2) | HI=0V, VCC=5V, HB-HS=5V, VIN=30V | 29.5 | 50 | ns | |
tMON | Delay Matching: LI high & HI low(2) | 2 | 8.0 | ns | ||
tMOFF | Delay Matching: LI low & HI high(2) | 2 | 8.0 | ns | ||
tPW | Minimum Input Pulse Width that Changes the Output | 10 | ns |