SNOSCY4E March   2015  – October 2018 LMG5200


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Block Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Propagation Delay and Mismatch Measurement
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Inputs
      2. 8.3.2 Start-up and UVLO
      3. 8.3.3 Bootstrap Supply Voltage Clamping
      4. 8.3.4 Level Shift
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. VCC Bypass Capacitor
        2. Bootstrap Capacitor
        3. Power Dissipation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Examples

Placements shown in Figure 14 and in the cross section of Figure 15 show the suggested placement of the device with respect to sensitive passive components, such as VIN, bootstrap capacitors (HS and HB) and VSS capacitors. Use appropriate spacing in the layout to reduce creepage and maintain clearance requirements in accordance with the application pollution level. Inner layers if present can be more closely spaced due to negligible pollution.

The layout must be designed to minimize the capacitance at the SW node. Use as small an area of copper as possible to connect the device SW pin to the inductor, or transformer, or other output load. Furthermore, ensure that the ground plane or any other copper plane has a cutout so that there is no overlap with the SW node, as this would effectively form a capacitor on the printed circuit board. Additional capacitance on this node reduces the advantages of the advanced packaging approach of the LMG5200 and may result in reduced performance. Figure 16, Figure 17, Figure 18, and Figure 19 show an example of how to design for minimal SW node capacitance on a four-layer board. In these figures, U1 is the LMG5200 device.

LMG5200 apps_layout_snoscy4.gifFigure 14. External Component Placement (Single Layer)
LMG5200 brd_xsection_snoscy4.gifFigure 15. Four-Layer Board Cross Section With Return Path Directly Underneath for Power Loop
LMG5200 layer1_cd_snoscy4.gifFigure 16. Top Layer
LMG5200 midlayer_cd_snoscy4.gifFigure 18. Middle Layer
LMG5200 gnd_cd_snoscy4.gifFigure 17. Ground Plane
LMG5200 bottom_cd_snoscy4.gifFigure 19. Bottom Layer
LMG5200 apps_layout2_snoscy4.gifFigure 20. External Component Placement (Double Layer PCB)
LMG5200 brd_xsection_2_snoscy4.gifFigure 21. Two-Layer Board Cross Section With Return Path

Two-layer boards are not recommended for use with LMG5200 device due to the larger power loop inductance. However, if design considerations allow only two board layers, place the input decoupling capacitors immediately behind the device on the back-side of the board to minimize loop inductance. Figure 20 and Figure 21 show a layout example for two-layer boards.