SNLS289D April   2008  – September 2015 LMH1982


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Supported Standards and Timing Formats
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. Free Run Mode
        2. Genlock Mode
          1. Genlock Mode State Diagram
            1. Loss of Reference (LOR)
              1. Free Run during LOR
              2. Holdover during LOR
    5. 7.5 Programming
      1. 7.5.1 I2C Interface Protocol
        1. Write Sequence
        2. Read Sequence
        3. I2C Enable Control Pin
    6. 7.6 Register Maps
      1. 7.6.1 I2C Interface Control Register Definitions
        1. Genlock and Input Reference Control Registers
        2. Genlock Status And Lock Control Register
        3. Input Control Register
        4. PLL 1 Divider Register
        5. PLL 4 Charge Pump Current Control Register
        6. Output Clock and TOF Control Register
        7. TOF Configuration Registers
        8. PLL 1, 2, 3 Charge Pump Current Control Registers
        9. Reserved Registers
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 148.35 MHz PLL Initialization Sequence
      2. 8.1.2 Enabling Genlock Mode
      3. 8.1.3 Output Disturbance While Output Alignment Mode Enabled
      4. 8.1.4 Evaluating the LMH1982
      5. 8.1.5 Input Reference
        1. Reference Frame Decoder
      6. 8.1.6 Output Clocks and TOF
        1. Programming the Output Clock Frequencies
        2. Programming the Output Format Timing
          1. Output TOF Clock
          2. Output Frame Timing
            1. HD Format TOF Generation Using a 27-MHz TOF Clock
          3. Reference Frame Timing
          4. Input-Output Frame Rate Ratio
          5. Output Frame Line Offset
        3. Programming the Output Initialization Sequence
          1. TOF Output Delay Considerations
          2. Output Clock Initialization Without TOF
        4. Output Behavior Upon Loss Of Reference
      7. 8.1.7 Reference And Pll Lock Status
        1. Reference Detection
          1. Programming the Loss of Reference (LOR) Threshold
        2. PLL Lock Detection
          1. Programming the PLL Lock Threshold
          2. PLL Lock Status Instability
      8. 8.1.8 Loop Response
        1. Loop Response Design Equations
          1. Loop Response Optimization Tips
          2. Loop Filter Capacitors
        2. Lock Time Considerations
        3. VCXO Considerations
        4. Free Run Output Jitter
    2. 8.2 Typical Applications
      1. 8.2.1 Analog Reference Genlock for Triple-Rate SDI Video
        1. Design Requirements
          1. Programming the PLL 1 Dividers
        2. Detailed Design Procedure
          1. Procedure for Designing the PLL 1 Dividers
      2. 8.2.2 SDI Reference Genlock for Triple-Rate SDI Video
      3. 8.2.3 Triple-Rate SDI Loop-through
      4. 8.2.4 Combined Genlock or Loop-Through for Triple-Rate SDI Video
  9. Power Supply Recommendations
    1. 9.1 Power Supply Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Two Simultaneous LVDS Output Clocks with Selectable Frequencies and Hi-Z Capability:
    • SD Clock: 27 MHz or 67.5 MHz
    • HD Clock: 74.25 MHz, 74.25/1.001 MHz,
      148.5 MHz or 148.5/1.001 MHz
  • Low-Jitter Output Clocks May Be Directly Connected to an FPGA Serializer to Meet SMPTE SDI Jitter Specifications
  • Top of Frame (TOF) Pulse with Programmable Output Format Timing and Hi-Z Capability
  • Two reference ports (A and B) With H and V Sync Inputs
  • Supports Cross-Locking of Input and Output Timing
  • External Loop Filter Allows Control of Loop Bandwidth, Jitter Transfer, and Lock Time Characteristics
  • Free Run or Holdover Operation on Loss of Reference
  • User-Defined Free Run Control Voltage Input
  • I2C Interface and Control Registers
  • 3.3-V and 2.5-V Supplies

2 Applications

  • Video Genlock and Synchronization
  • FPGA SDI SerDes Recovered Clock Generation
  • Triple Rate 3G/HD/SD-SDI SerDes
  • Video Capture, Conversion, Editing and Distribution
  • Video Displays and Projectors
  • Broadcast and Professional Video Equipment

3 Description

The LMH1982 device is a multi-rate video clock generator ideal for use in a wide range of 3-Gbps (3G), high-definition (HD), and standard-definition (SD) video applications, such as video synchronization, serial digital interface (SDI) serializer and deserializer (SerDes), video conversion, video editing, and other broadcast and professional video systems.

The LMH1982 can generate two simultaneous SD and HD clocks and a Top of Frame (TOF) pulse. In genlock mode, the device's phase locked loops (PLLs) can synchronize the output signals to H sync and V sync input signals applied to either of the reference ports. The input reference can have analog timing from Texas Instrument's LMH1981 multi-format video sync separator or digital timing from an SDI deserializer and should conform to the major SD and HD standards. When a loss of reference occurs, the device can default to free run operation where the output timing accuracy will be determined by the external bias on the free run control voltage input.

The LMH1982 can replace discrete PLLs and field-programmable gate array (FPGA) PLLs with multiple voltage controlled crystal oscillators (VCXOs). Only one 27.0000 MHz VCXO and loop filter are externally required for genlock mode. The external loop filter as well as programmable PLL parameters can provide narrow loop bandwidths to minimize jitter transfer. HD clock output jitter as low as 40 ps peak-to-peak can help designers using FPGA SerDes meet stringent SDI output jitter specifications.

The LMH1982 is offered in a space-saving 5 mm x 5 mm 32-pin WQFN package and provides low total power consumption of about 250 mW (typical).

Device Information(1)

LMH1982 WQFN (32) 5.00 mm × 5.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Genlock Application

LMH1982 30052407.gif

Typical Loop Filter Topology

LMH1982 30052439.gif