Product details

Function Clock generator Number of outputs 2 Output frequency (Max) (MHz) 148.5 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Input type LVCMOS Output type LVDS Operating temperature range (C) 0 to 70 Features Multi-rate video clock generator with Genlock Rating Catalog
Function Clock generator Number of outputs 2 Output frequency (Max) (MHz) 148.5 Core supply voltage (V) 2.5, 3.3 Output supply voltage (V) 2.5, 3.3 Input type LVCMOS Output type LVDS Operating temperature range (C) 0 to 70 Features Multi-rate video clock generator with Genlock Rating Catalog
WQFN (RTV) 32 25 mm² 5 x 5
  • Two Simultaneous LVDS Output Clocks with
    Selectable Frequencies and Hi-Z Capability:
    • SD Clock: 27 MHz or 67.5 MHz
    • HD Clock: 74.25 MHz, 74.25/1.001 MHz,
      148.5 MHz or 148.5/1.001 MHz
  • Low-Jitter Output Clocks May Be Directly
    Connected to an FPGA Serializer to Meet SMPTE
    SDI Jitter Specifications
  • Top of Frame (TOF) Pulse with Programmable
    Output Format Timing and Hi-Z Capability
  • Two reference ports (A and B) With H and V Sync
    Inputs
  • Supports Cross-Locking of Input and Output
    Timing
  • External Loop Filter Allows Control of Loop
    Bandwidth, Jitter Transfer, and Lock Time
    Characteristics
  • Free Run or Holdover Operation on Loss of
    Reference
  • User-Defined Free Run Control Voltage Input
  • I2C Interface and Control Registers
  • 3.3-V and 2.5-V Supplies
  • Two Simultaneous LVDS Output Clocks with
    Selectable Frequencies and Hi-Z Capability:
    • SD Clock: 27 MHz or 67.5 MHz
    • HD Clock: 74.25 MHz, 74.25/1.001 MHz,
      148.5 MHz or 148.5/1.001 MHz
  • Low-Jitter Output Clocks May Be Directly
    Connected to an FPGA Serializer to Meet SMPTE
    SDI Jitter Specifications
  • Top of Frame (TOF) Pulse with Programmable
    Output Format Timing and Hi-Z Capability
  • Two reference ports (A and B) With H and V Sync
    Inputs
  • Supports Cross-Locking of Input and Output
    Timing
  • External Loop Filter Allows Control of Loop
    Bandwidth, Jitter Transfer, and Lock Time
    Characteristics
  • Free Run or Holdover Operation on Loss of
    Reference
  • User-Defined Free Run Control Voltage Input
  • I2C Interface and Control Registers
  • 3.3-V and 2.5-V Supplies

The LMH1982 device is a multi-rate video clock generator ideal for use in a wide range of 3-Gbps (3G), high-definition (HD), and standard-definition (SD) video applications, such as video synchronization, serial digital interface (SDI) serializer and deserializer (SerDes), video conversion, video editing, and other broadcast and professional video systems.

The LMH1982 can generate two simultaneous SD and HD clocks and a Top of Frame (TOF) pulse. In genlock mode, the device's phase locked loops (PLLs) can synchronize the output signals to H sync and V sync input signals applied to either of the reference ports. The input reference can have analog timing from Texas Instrument's LMH1981 multi-format video sync separator or digital timing from an SDI deserializer and should conform to the major SD and HD standards. When a loss of reference occurs, the device can default to free run operation where the output timing accuracy will be determined by the external bias on the free run control voltage input.

The LMH1982 can replace discrete PLLs and field-programmable gate array (FPGA) PLLs with multiple voltage controlled crystal oscillators (VCXOs). Only one 27.0000 MHz VCXO and loop filter are externally required for genlock mode. The external loop filter as well as programmable PLL parameters can provide narrow loop bandwidths to minimize jitter transfer. HD clock output jitter as low as 40 ps peak-to-peak can help designers using FPGA SerDes meet stringent SDI output jitter specifications.

The LMH1982 is offered in a space-saving 5 mm × 5 mm 32-pin WQFN package and provides low total power consumption of about 250 mW (typical).

The LMH1982 device is a multi-rate video clock generator ideal for use in a wide range of 3-Gbps (3G), high-definition (HD), and standard-definition (SD) video applications, such as video synchronization, serial digital interface (SDI) serializer and deserializer (SerDes), video conversion, video editing, and other broadcast and professional video systems.

The LMH1982 can generate two simultaneous SD and HD clocks and a Top of Frame (TOF) pulse. In genlock mode, the device's phase locked loops (PLLs) can synchronize the output signals to H sync and V sync input signals applied to either of the reference ports. The input reference can have analog timing from Texas Instrument's LMH1981 multi-format video sync separator or digital timing from an SDI deserializer and should conform to the major SD and HD standards. When a loss of reference occurs, the device can default to free run operation where the output timing accuracy will be determined by the external bias on the free run control voltage input.

The LMH1982 can replace discrete PLLs and field-programmable gate array (FPGA) PLLs with multiple voltage controlled crystal oscillators (VCXOs). Only one 27.0000 MHz VCXO and loop filter are externally required for genlock mode. The external loop filter as well as programmable PLL parameters can provide narrow loop bandwidths to minimize jitter transfer. HD clock output jitter as low as 40 ps peak-to-peak can help designers using FPGA SerDes meet stringent SDI output jitter specifications.

The LMH1982 is offered in a space-saving 5 mm × 5 mm 32-pin WQFN package and provides low total power consumption of about 250 mW (typical).

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Technical documentation

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Type Title Date
* Data sheet LMH1982 Multi-Rate Video Clock Generator With Genlock datasheet (Rev. D) 30 Sep 2015
Selection guide Broadcast and Professional Video Interface Solutions (Rev. E) 05 Apr 2017
Technical article How to select an optimal clocking solution for your FPGA-based design 09 Dec 2015
Technical article Clocking sampled systems to minimize jitter 31 Jul 2014
Technical article Timing is Everything: How to optimize clock distribution in PCIe applications 28 Mar 2014
User guide AN-1841 LMH1982 Evaluation Board User Guide (Rev. A) 26 Apr 2013
Application note Demonst SMPTE-Compliant SDI Out Jittr Using LMH1982 & Virtx-5 GTP Xmittr (Rev. A) 26 Apr 2013
Application note Triple Rate SDI IP FPGA Resource Utilization on SDXILEVK/AES-EXP-SDI-G Ref Dsgn (Rev. A) 26 Apr 2013
More literature LMH1982 SD/HD Video Clock and Timing Generator with Genlock Capability 25 Jan 2012
Design guide Broadcast Video Owner's Manual 17 Nov 2006

Design & development

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Evaluation board

LMH1982SQEEVAL — LMH1982 Multi-Rate Video Clock Generator with LMH1981 HD/SD Video Sync Separator EVM

The LMH1982 evaluation board platform was designed by Texas Instruments to demonstrate the excellent clock jitter performance of the LMH1982 multi-rate video clock and timing generator in a genlock application with the LMH1981 multi-format video sync separator. The evaluation platform consists of (...)

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Support software

LMH1982APP-SW — LMH1982 Software Setup - Multi-Rate Video Clock Generator with Genlock

Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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