SNAS669E September 2015 – April 2018 LMK03318
PRODUCTION DATA.
The MUTELVL2 register determines the Output Driver during mute for output drivers 4 to 7.
Bit # | Field | Type | Reset | EEPROM | Description | ||
---|---|---|---|---|---|---|---|
[7:6] | CH7_MUTE_LVL[1:0] | RW | 0x1 | Y | Channel 7 Output Driver Mute Level. CH7_MUTE_LVL determines the configuration of the CH7 Output Driver during mute as shown in the following table and is recommended to be set to 0x3. CH7_MUTE_LVL does not determine whether the CH7 driver is muted or not, instead this is determined by the CH_7_MUTE register bit. | ||
CH7_MUTE_LVL | DIFF MODE | CMOS MODE | |||||
0 (0x0) | CH7 Mute Bypass | CH7 Mute Bypass | |||||
1 (0x1) | Powerdown, output goes to Vcm | Out_P Normal Operation, Out_N Force Output Low | |||||
2 (0x2) | Force output High | Out_P Force Output Low, Out_N Normal Operation | |||||
3 (0x3) | Force the positive output node to the internal regulator output voltage rail (when AC coupled to load) and the negative output node to the GND rail | Out_P Force Output Low, Out_N Force Output Low | |||||
[5:4] | CH6_MUTE_LVL[1:0] | RW | 0x1 | Y | Channel 6 Output Driver Mute Level. CH6_MUTE_LVL determines the configuration of the CH6 Output Driver during mute as shown in the following table and is recommended to be set to 0x3. CH6_MUTE_LVL does not determine whether the CH6 driver is muted or not, instead this is determined by the CH_6_MUTE register bit. | ||
CH6_MUTE_LVL | DIFF MODE | CMOS MODE | |||||
0 (0x0) | CH6 Mute Bypass | CH6 Mute Bypass | |||||
1 (0x1) | Powerdown, output goes to Vcm | Out_P Normal Operation, Out_N Force Input Low | |||||
2 (0x2) | Force output High | Out_P Force Output Low, Out_N Normal Operation | |||||
3 (0x3) | Force the positive output node to the internal regulator output voltage rail (when AC coupled to load) and the negative output node to the GND rail | Out_P Force Output Low, Out_N Force Output Low | |||||
[3:2] | CH5_MUTE_LVL[1:0] | RW | 0x1 | Y | Channel 5 Output Driver Mute Level. CH5_MUTE_LVL determines the configuration of the CH5 Output Driver during mute as shown in the following table and is recommended to be set to 0x3. CH5_MUTE_LVL does not determine whether the CH5 driver is muted or not, instead this is determined by the CH_5_MUTE register bit. | ||
CH5_MUTE_LVL | DIFF MODE | CMOS MODE | |||||
0 (0x0) | CH5 Mute Bypass | CH5 Mute Bypass | |||||
1 (0x1) | Powerdown, output goes to Vcm | Out_P Normal Operation, Out_N Force Output Low | |||||
2 (0x2) | Force output High | Out_P Force Output Low, Out_N Normal Operation | |||||
3 (0x3) | Force the positive output node to the internal regulator output voltage rail (when AC coupled to load) and the negative output node to the GND rail | Out_P Force Output Low, Out_N Force Output Low | |||||
[1:0] | CH4_MUTE_LVL[1:0] | RW | 0x1 | Y | Channel 4 Output Driver Mute Level. CH4_MUTE_LVL determines the configuration of the CH4 Output Driver during mute as shown in the following table and is recommended to be set to 0x3. CH4_MUTE_LVL does not determine whether the CH4 driver is muted or not, instead this is determined by the CH_4_MUTE register bit. | ||
CH4_MUTE_LVL | DIFF MODE | CMOS MODE | |||||
0 (0x0) | CH4 Mute Bypass | CH4 Mute Bypass | |||||
1 (0x1) | Powerdown, output goes to Vcm | Out_P Normal Operation, Out_N Force Output Low | |||||
2 (0x2) | Force output High | Out_P Force Output Low, Out_N Normal Operation | |||||
3 (0x3) | Force the positive output node to the internal regulator output voltage rail (when AC coupled to load) and the negative output node to the GND rail | Out_P Force Output Low, Out_N Force Output Low |