SNAS822C September   2021  – February 2026 LMK1D2102 , LMK1D2104

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Inputs
    4. 8.4 Device Functional Modes
      1. 8.4.1 LVDS Output Termination
      2. 8.4.2 Input Termination
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2 Detailed Design Procedure

See Section 8.4.2 for proper input terminations, dependent on single-ended or differential inputs.

See Section 8.4.1 for output termination schemes depending on the receiver application.

TI recommends unused outputs to be terminated differentially with a 100Ω resistor for optimum performance, although unterminated outputs are also okay but results in slight degradation in performance (Output AC common-mode VOS ) in the outputs being used.

In the application example described in the previous section Figure 9-1, the ADC clock and SYSREF clocks require different output interfacing schemes. Power supply filtering and bypassing is critical for low-noise applications.

In case of common-mode mismatch between the output voltage of the LMK1D210x and the receiver, AC coupling can be used to circumvent mismatch. However, in certain applications, AC-coupling the LMK1D210x outputs to the receiver is not necessary possible due to the settling time associated with this AC coupling network (High-pass filter) which can result in non-deterministic behavior during the initial transients. For such applications, DC-coupling is necessary for the outputs and thus requires a scheme which can overcome the inherent mismatch between the common-mode of the driver and receiver.

The application note Interfacing LVDS Driver With a Sub-LVDS Receiver discusses how to interface between a LVDS driver and sub-LVDS receiver. The same concept can be applied to interface the LMK1D210x outputs to a receiver which has lower common-mode.

LMK1D2102 LMK1D2104 Schematic for DC-coupling LMK1D210x With Lower Common-mode ReceiverFigure 9-2 Schematic for DC-coupling LMK1D210x With Lower Common-mode Receiver

The Figure 9-2 illustrates the resistor divider network for stepping down the common mode as explained in the previously mentioned application note. The resistors R1, R2 and R3 are selected according to the input common mode requirements of the receiver. As highlighted before, user needs to make sure that the reduced swing is able to meet the requirements of the receiver.