Product details

Function Clock buffer, Differential Additive RMS jitter (Typ) (fs) 50 Output frequency (Max) (MHz) 2000 Number of outputs 4 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Features Dual 1:2 fanout, Universal inputs, Output enable control Operating temperature range (C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
Function Clock buffer, Differential Additive RMS jitter (Typ) (fs) 50 Output frequency (Max) (MHz) 2000 Number of outputs 4 Output supply voltage (V) 1.8, 2.5, 3.3 Core supply voltage (V) 1.8, 2.5, 3.3 Output skew (ps) 20 Features Dual 1:2 fanout, Universal inputs, Output enable control Operating temperature range (C) -40 to 105 Rating Catalog Output type LVDS Input type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL
VQFN (RGT) 16 9 mm² 3 x 3
  • High-performance LVDS clock buffer family: up to 2 GHz
    • Dual 1:2 differential buffer
    • Dual 1:4 differential buffer
  • Supply voltage: 1.71 V to 3.465 V
  • Low additive jitter: < max 60 fs RMS in 12-kHz to 20-MHz @ 156.25 MHz
    • Very low phase noise floor: -164 dBc/Hz (typical)

  • Very low propagation delay < 575 ps max

  • Output skew of 20 ps max

  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels.
  • LVDS reference voltage, VAC_REF, available for capacitive coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packaged in
    • LMK1D2102: 3-mm x 3-mm, 16-Pin VQFN

    • LMK1D2104: 5-mm x 5-mm, 28-Pin VQFN

  • High-performance LVDS clock buffer family: up to 2 GHz
    • Dual 1:2 differential buffer
    • Dual 1:4 differential buffer
  • Supply voltage: 1.71 V to 3.465 V
  • Low additive jitter: < max 60 fs RMS in 12-kHz to 20-MHz @ 156.25 MHz
    • Very low phase noise floor: -164 dBc/Hz (typical)

  • Very low propagation delay < 575 ps max

  • Output skew of 20 ps max

  • Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal levels.
  • LVDS reference voltage, VAC_REF, available for capacitive coupled inputs
  • Industrial temperature range: –40°C to 105°C
  • Packaged in
    • LMK1D2102: 3-mm x 3-mm, 16-Pin VQFN

    • LMK1D2104: 5-mm x 5-mm, 28-Pin VQFN

The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of up to 8 pairs of differential LVDS clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input and up to 4 LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML or LVCMOS.

The LMK1D210x is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage as shown in Figure 8-6 must be applied to the unused negative input pin.

Using the control pin (EN), output banks can either be enabled or disabled. If this pin is left open, two buffers with all outputs are enabled, if switched to a logic "0", both banks with all outputs are disabled (static logic "0"), if switched to a logic "1", one bank and its outputs are disabled while another bank with its outputs are enabled. The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature). The LMK1D210x package variant is shown in the table below:

The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of up to 8 pairs of differential LVDS clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one input and up to 4 LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML or LVCMOS.

The LMK1D210x is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage as shown in Figure 8-6 must be applied to the unused negative input pin.

Using the control pin (EN), output banks can either be enabled or disabled. If this pin is left open, two buffers with all outputs are enabled, if switched to a logic "0", both banks with all outputs are disabled (static logic "0"), if switched to a logic "1", one bank and its outputs are disabled while another bank with its outputs are enabled. The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature). The LMK1D210x package variant is shown in the table below:

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* Data sheet LMK1D210x Low Additive Jitter LVDS Buffer datasheet 16 Sep 2021

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