SNOSCX0A June   2013  – December 2014 LMP92064

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Sense Input Channel
      2. 7.3.2 Current Sense Input Channel Common-Mode and Differential Voltage Range (Dynamic Range Considerations)
      3. 7.3.3 Voltage Sense Input Channel
      4. 7.3.4 Reference
      5. 7.3.5 Reset
      6. 7.3.6 Device Power-Up Sequence
    4. 7.4 Device Functional Modes
      1. 7.4.1 ADC Operation
    5. 7.5 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Digital Isolators
        2. 8.2.2.2 Supply Voltage for the LMP92064
        3. 8.2.2.3 Series Resistor for the Shunt Regulator
        4. 8.2.2.4 Voltage Channel Input Resistor Divider
        5. 8.2.2.5 Sense Resistor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Current Input Error Sources
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Power Supply Recommendations

To decouple the LMP92064 from AC noise on the power supply, it is recommended to use a 0.1-μF bypass capacitor between the VDD and GND pins. This capacitor should be placed as close as possible to the supply pins. In some cases an additional 10-μF bypass capacitor may further reduce the supply noise. In addition, the VDIG power pin should also be decoupled to DGND with a 0.1-μF bypass capacitor. Do not forget that these capacitors must be rated for the full supply voltage (2x the maximum voltage is recommended for the capacitor working voltage rating).