SNOSD09 September   2015 LMV7275-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings LMV7275-Q1
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  1.8-V Electrical Characteristics
    6. 6.6  1.8-V AC Electrical Characteristics
    7. 6.7  2.7-V Electrical Characteristics
    8. 6.8  2.7-V AC Electrical Characteristics
    9. 6.9  5-V Electrical Characteristics
    10. 6.10 5-V AC Electrical Characteristics
    11. 6.11 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Rail-to-Rail Input Stage
      2. 7.3.2 Output Stage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Capacitive and Resistive Loads
      2. 7.4.2 Noise
      3. 7.4.3 Hysteresis
        1. Non-inverting Comparator With Hysteresis
        2. Inverting Comparator With Hysteresis
      4. 7.4.4 Zero Crossing Detector
        1. Zero Crossing Detector With Hysteresis
      5. 7.4.5 Threshold Detector
      6. 7.4.6 Universal Logic Level Shifter
      7. 7.4.7 OR'ING the Output
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Square Wave Oscillator
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      2. 8.2.2 Positive Peak Detector
      3. 8.2.3 Negative Peak Detector
      4. 8.2.4 Window Detector
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Circuit Techniques for Avoiding Oscillations in Comparator Applications
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LMV7275-Q1 is a single-supply comparator with 880 ns of propagation delay and only 12 µA of supply current.

8.2 Typical Applications

8.2.1 Square Wave Oscillator

LMV7275-Q1 20064056.gif Figure 27. Square Wave Oscillator Application Design Requirements

A typical application for a comparator is as a square wave oscillator. Figure 27 generates a square wave whose period is set by the RC time constant of the capacitor C1and resistor R4. The maximum frequency is limited by the large signal propagation delay of the comparator, and by the capacitive loading at the output, which limits the output slew rate. Detailed Design Procedure

To analyze the circuit, consider it when the output is high. That implies that the inverted input (VC) is lower than the Non-Inverting input (VA).

LMV7275-Q1 20064057.png Figure 28. Squarewave Oscillator Timing Thresholds

This causes the C1 to get charged through R4, and the voltage VC increases till it is equal to the Non-Inverting input. The value of VA at this point is

Equation 9. LMV7275-Q1 20064058.gif

If R1 = R2 = R3, then VA1 = 2VCC/3

At this point the comparator switches pulling down the output to the negative rail. The value of VA at this point is

Equation 10. LMV7275-Q1 20064059.gif

If R1 = R2 = R3, then VA2 = VCC/3

The capacitor C1 now discharges through R4, and the voltage VC decreases till it is equal to VA2, at which point the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it takes to discharge C1 from 2VCC/3 to VCC/3, which is given by R4C1.ln2. Hence the formula for the frequency is:

F = 1/(2·R4·C1·ln2) Application Curve

Figure 29 shows the simulated results of an oscillator using the following values:

  1. R1 = R2 = R3 = R4 = 100 kΩ
  2. C1 = 750 pF, CL = 20 pF
  3. V+ = 5 V, V- = GND
  4. CSTRAY (not shown) from Va to GND = 10 pF

LMV7275-Q1 OSC_RSLT_GRAPH.png Figure 29. Square Wave Oscillator Output Waveforms

8.2.2 Positive Peak Detector

LMV7275-Q1 Pos_Pk_Det.gif Figure 30. Positive Peak Detector

The positive peak detector is basically the comparator operated as a unity gain follower with a large holding capacitor from the output to ground. A transistor is added to the output to provide a low impedance current source. The upper output swing is limited by the emitter-base forward voltage. This allows capture of the most positive input signal between 0 V and (V+) - 0.7V.

When the output of the comparator goes high, current is passed through the transistor to charge up the capacitor. The only discharge path will be the 1-MΩ resistor shunting C1 and any load that is connected to the output. The decay time can be altered simply by changing the 1-MΩ resistor.

8.2.3 Negative Peak Detector

LMV7275-Q1 Neg_Pk_Det_Neg_Supply.gif Figure 31. Negative Peak Detector for Negative Supply

The Negative Peak Detector circuit will store the peak negative voltage below ground ( 0 V to V-). For the negative detector, the output transistor acts as a low-impedance current sink.

When VIN is more negative than VOUT, the output transistor will conduct and pull the output to -VCC, charging C1. Charging stops when C1 reaches the same level as VIN. Because there is no pull-up resistor, the only discharge path will be the 1-MΩ resistor and any load impedance applied. Therefore, the decay time is set by varying the 1-MΩ resistor. Be sure to observe the polarity of C1!

LMV7275-Q1 Neg_Pk_Det_Pos_Supply.gif Figure 32. Negative Peak Detector for Positive Supply

An alternate positive supply version is shown in Figure 32 that will capture the lowest applied VIN value between V+ and ground (V+ to 0V).

The output of either version should be buffered by a high-impedance follower stage to prevent loading of the RC circuit.

8.2.4 Window Detector

LMV7275-Q1 20201347.gif Figure 33. Window Detector

A window detector monitors the input signal to determine if it falls between two voltage levels. Both outputs are true (high) when VREF1 < VIN < VREF2

LMV7275-Q1 20201348.gif Figure 34. Window Detector Output Signal

The comparator outputs A and B are high only when VREF1 < VIN < VREF2, or within the window, where these are defined as:

Equation 11. VREF1 = R3 / (R1 + R2 + R3) × V+
Equation 12. VREF2 = (R2 + R3) / (R1 + R2 + R3) × V+

To determine if the input signal falls outside of the two voltage levels, both inputs on each comparators can be reversed to invert the logic.

The outputs should be tied together and use a shared pull-up resistor for a common logic output. If individual limit outputs are needed, then each output will require it's own pull-up resistor.

Other names for window detectors are: threshold detector, level detector, and amplitude trigger or detector.