7.3.1 Rail-to-Rail Input Stage

The LMV7275-Q1 has an input common mode voltage range (V_CM) of −0.1V below the V⁻ to 0.1 V above V⁺. This is achieved by using paralleled PNP and NPN differential input pairs. When the V_CM is near V⁺, the NPN pair is on and the PNP pair is off. When the V_CM is near V⁻, the NPN pair is off and the PNP pair is on. The crossover point between the NPN and PNP input stages is around 950mV from V⁺. Because each input stage has its own offset voltage (V_OS), the V_OS of the comparator becomes a function of the V_CM. See curves for V_OS vs. V_CM in the Typical Characteristics section. In application design, it is recommended to keep the V_CM away from the crossover point to avoid problems. The wide input voltage range makes LMV7275-Q1 ideal in power supply monitoring circuits, where the comparators are used to sense signals close to ground and power supplies.

7.3.2 Output Stage

Figure 19. LMV7275-Q1 Open-Drain Output

The LMV7275-Q1 has an open-drain output that requires a pull-up resistor to a positive supply voltage for the output to operate properly. When the internal output transistor is off, the output voltage will be pulled up to the external positive voltage (V₂₊) by the external pull-up resistor. This allows the output to be OR'ed with other open-drain outputs on the same bus.

The output pull-up resistor may be connected to any voltage level between V- and V+ for level shifting applications.

7.4.1 Capacitive and Resistive Loads

The propagation delay on the rising edge of the LMV7275-Q1 depends on the load resistance and capacitance values.

7.4.2 Noise

Most comparators have rather low gain. This allows the output to alternate between high and low when the input signal changes slowly. The result is the output may oscillate between high and low when the differential input is near zero and triggers on noise. The high gain of this comparator eliminates this problem. Less than 1 μV of change on the input will drive the output from one rail to the other rail. If the input signal is noisy, the output cannot ignore the noise unless some hysteresis is provided by positive feedback. (See Hysteresis.)

7.4.3 Hysteresis

It is a standard procedure to use hysteresis (positive feedback) around a comparator to prevent oscillation due to the comparator triggering its own noise on slowly ramping signals. The following sections will describe various ways to apply hysteresis.

7.4.3.1 Non-inverting Comparator With Hysteresis

Non-inverting comparator with hysteresis requires a two resistor network, and a voltage reference (V_ref) at the inverting input. When V_in is low, the output is also low. For the output to switch from low to high, V_in must rise up to V_in1 where V_in1 is calculated by:

Equation 1.

When V_in is high, the output is also high. To make the comparator switch back to its low state, V_in must equal V_ref before V_A will again equal V_ref. V_in can be calculated by:

Equation 2.

The hysteresis of this circuit is the difference between V_in1 and V_in2.

Equation 3. ΔV_in = V_CCR₁/R₂

Figure 20. Non-Inverting Comparator With Hysteresis

7.4.3.2 Inverting Comparator With Hysteresis

The inverting comparator with hysteresis requires a three resistor network that are referenced to the supply voltage V_CC of the comparator. When V_in at the inverting input is less than V_a, the voltage at the non-inverting node of the comparator (V_in < V_a), the output voltage is high (for simplicity assume V_O switches as high as V_CC). The three network resistors can be represented as R₁//R₃ in series with R₂. The lower input trip voltage V_a1 is defined as:

Equation 4.

When V_in is greater than V_a (V_in > V_a), the output voltage is low very close to ground. In this case the three network resistors can be presented as R₂//R₃ in series with R₁. The upper trip voltage V_a2 is defined as:

Equation 5.

The total hysteresis provided by the network is defined as:

Equation 6. ΔV_a = V_a1 - V_a2

To assure that the comparator will always switch fully to V_CC and not be pulled down by the load the resistors values should be chosen as follow:

Equation 7. R_PULL-UP << R_LOAD

Equation 8. and R₁ > R_PULL-UP.

Figure 21. Inverting Comparator With Hysteresis

7.4.4 Zero Crossing Detector

Figure 22. Simple Zero Crossing Detector

In a zero crossing detector circuit, the inverting input is connected to ground and the Non-Inverting input is connected to a 100 mV_PP AC signal. As the signal at the Non-Inverting input crosses 0 V, the output of the comparator changes state.

R_PROT is an optional input protection resistor to limit the current should the input voltage exceed the supply rails. R_PROT should be a minimum of 1 kΩ per volt of expected over-voltage and limit the current to less than ±1mA under worst case fault conditions.

7.4.4.1 Zero Crossing Detector With Hysteresis

Figure 23. Zero Crossing Detector With Hysteresis

To improve switching times and centering the input threshold to ground a small amount of positive feedback is added to the circuit. Voltage divider R₄ and R₅ establishes a reference voltage, V₁, at the positive input. By making the series resistance, R₁ plus R₂ equal to R₅, the switching condition, V₁ = V₂, will be satisfied when V_IN = 0.

The positive feedback resistor, R₆, is made very large (with respect to R₅ || R₆ = 2000 R₅). The resultant hysteresis established by this network is very small (ΔV₁ < 10 mV) but it is sufficient to insure rapid output voltage transitions.

Diode D₁ is used to insure that the inverting input terminal of the comparator never goes below approximately −100 mV. As the input terminal goes negative, D₁ will forward bias, clamping the node between R₁ and R₂ to approximately −300 mV. This sets up a voltage divider with R₂ and R₃ preventing V₂ from going below ground. The maximum negative input overdrive is limited by the current handling ability of D₁.

7.4.5 Threshold Detector

Figure 24. Threshold Detector

Instead of tying the inverting input to 0 V, the inverting input can be tied to a reference voltage. As the input on the Non-Inverting input passes the V_REF threshold, the output of the comparator changes state. It is important to use a stable reference voltage to ensure a consistent switching point.

7.4.6 Universal Logic Level Shifter

Figure 25. Logic Level Shifter

The output of LMV7275-Q1 is an unconnected drain of an NMOS device, which can be pulled up, through a resistor, to any desired output level below the comparators power supply voltage (V_B ≤ V_CC). Hence, the following simple circuit works as a universal logic level shifter, pulling up the signal to the desired level.

For example, V_A could be the 5-V analog supply voltage, where V_B could be the 3.3-V supply of the processor. The output will now be compatible with the 3.3-V logic.

7.4.7 OR'ING the Output

Figure 26. OR’ing the Outputs

Open-drain outputs may be tied together, pulled up to V_D by a common resistor to provide an output OR'ing function. If any of the comparator outputs goes low, the output V_O goes low.