SNOSAG6G Data sheet

SNOSAG6G September 2005 – October 2015 LMV791 , LMV792

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

DGS|10
- MPDS035C

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

See ⁽¹⁾⁽⁷⁾

		MIN	MAX	UNIT
V_IN differential			±0.3	V
Supply voltage (V⁺ – V⁻)			6	V
Input/Output pin voltage		V⁺ + 0.3	V⁻ − 0.3	V
Junction temperature⁽²⁾			150	°C
Soldering information	Infrared or convection (20 sec)		235	°C
Soldering information	Wave soldering lead temperature (10 sec)		260	°C
Storage temperature, T_stg		−65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The maximum power dissipation is a function of T_J(MAX), θ_JA. The maximum allowable power dissipation at any ambient temperature is P_D = (T_J(MAX) - T_A)/θ_JA. All numbers apply for packages soldered directly onto a PCB.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾⁽³⁾	±2000	V
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000
		Machine model⁽⁴⁾	±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) Human Body Model is 1.5 kΩ in series with 100 pF.

(4) Machine Model is 0 Ω in series with 200 pF

6.3 Recommended Operating Conditions

		MIN	MAX	UNIT
Temperature⁽¹⁾		−40	125	°C
Supply voltage (V⁺ – V⁻)	−40°C ≤ T_J ≤ 125°C	2	5.5	V
Supply voltage (V⁺ – V⁻)	0°C ≤ T_J ≤ 125°C	1.8	5.5	V

(1) The maximum power dissipation is a function of T_J(MAX), θ_JA. The maximum allowable power dissipation at any ambient temperature is P_D = (T_J(MAX) - T_A)/θ_JA. All numbers apply for packages soldered directly onto a PCB.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LMV791	LMV792	UNIT
		DDC (SOT-23)	DGS (VSSOP)
		6 PINS	10 PINS
R_θJA	Junction-to-ambient thermal resistance⁽²⁾	191.8	179.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	68.1	70.5	°C/W
R_θJB	Junction-to-board thermal resistance	36.9	99.7	°C/W
ψ_JT	Junction-to-top characterization parameter	2.2	11.6	°C/W
ψ_JB	Junction-to-board characterization parameter	36.5	98.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 2.5-V Electrical Characteristics

Unless otherwise specified, all limits are ensured for T_J = 25°C, V⁺ = 2.5 V, V⁻ = 0 V, V_CM = V⁺/2 = V_O, V_EN = V⁺.

PARAMETER		TEST CONDITIONS			MIN⁽²⁾	TYP⁽¹⁾	MAX⁽²⁾	UNIT
V_OS	Input offset voltage	T_J = 25 °C				0.1	±1.35	mV
V_OS	Input offset voltage	−40°C ≤ T_J ≤ 125°C					±1.65	mV
TC V_OS	Input offset voltage temperature drift	LMV791⁽³⁾				−1		μV/°C
TC V_OS	Input offset voltage temperature drift	LMV792⁽³⁾				−1.8		μV/°C
I_B	Input bias current	V_CM = 1 V⁽⁴⁾ ⁽⁵⁾	T_J = 25 °C			0.05	1	pA
			−40°C ≤ T_J ≤ 85 °C				25
			−40°C ≤ T_J ≤ 125 °C				100
I_OS	Input offset current	V_CM = 1 V⁽⁵⁾				10		fA
CMRR	Common-mode rejection ratio	0 V ≤ V_CM ≤ 1.4 V	T_J = 25 °C		80	94		dB
CMRR	Common-mode rejection ratio	0 V ≤ V_CM ≤ 1.4 V	−40°C ≤ T_J ≤ 125°C		75			dB
PSRR	Power supply rejection ratio	2.0V ≤ V⁺ ≤ 5.5V, V_CM = 0 V	T_J = 25 °C		80	100		dB
		2.0V ≤ V⁺ ≤ 5.5V, V_CM = 0 V	−40°C ≤ T_J ≤ 125°C		75
		1.8 V ≤ V⁺ ≤ 5.5 V, V_CM = 0 V			80	98
CMVR	Common-mode voltage range	CMRR ≥ 60 dB	T_J = 25 °C		−0.3		1.5	V
CMVR	Common-mode voltage range	CMRR ≥ 55 dB	−40°C ≤ T_J ≤ 125°C		−0.3		1.5	V
A_VOL	Open-loop voltage gain	V_OUT = 0.15 V to 2.2 V, R_LOAD = 2 kΩ to V⁺/2	LMV791	T_J = 25 °C	85	98		dB
			LMV791	−40°C ≤ T_J ≤ 125°C	80
			LMV792	T_J = 25 °C	82	92
			LMV792	−40°C ≤ T_J ≤ 125°C	78
		V_OUT = 0.15 V to 2.2 V, R_LOAD = 10 kΩ to V⁺/2	T_J = 25 °C		88	110
		V_OUT = 0.15 V to 2.2 V, R_LOAD = 10 kΩ to V⁺/2	−40°C ≤ T_J ≤ 125°C		84
V_OUT	Output voltage swing high	R_LOAD = 2 kΩ to V⁺/2	T_J = 25 °C			25	75	mV from either rail
		R_LOAD = 2 kΩ to V⁺/2	−40°C ≤ T_J ≤ 125°C				82
		R_LOAD = 10 kΩ to V⁺/2	T_J = 25 °C			20	65
		R_LOAD = 10 kΩ to V⁺/2	−40°C ≤ T_J ≤ 125°C				71
	Output voltage swing low	R_LOAD = 2 kΩ to V⁺/2	T_J = 25 °C			30	75
		R_LOAD = 2 kΩ to V⁺/2	−40°C ≤ T_J ≤ 125°C				78
		R_LOAD = 10 kΩ to V⁺/2	T_J = 25 °C			15	65
		R_LOAD = 10 kΩ to V⁺/2	−40°C ≤ T_J ≤ 125°C				67
I_OUT	Output current	Sourcing to V⁻ V_IN = 200 mV⁽⁶⁾	T_J = 25 °C		35	47		mA
		Sourcing to V⁻ V_IN = 200 mV⁽⁶⁾	−40°C ≤ T_J ≤ 125°C		28
		Sinking to V⁺ V_IN = –200 mV⁽⁶⁾	T_J = 25 °C		7	15
		Sinking to V⁺ V_IN = –200 mV⁽⁶⁾	−40°C ≤ T_J ≤ 125°C		5
I_S	Supply current per amplifier	Enable mode V_EN ≥ 2.1 V	LMV791	T_J = 25 °C		0.95	1.3	mA
			LMV791	−40°C ≤ T_J ≤ 125°C			1.65
			LMV792 per channel	T_J = 25 °C		1.1	1.50
			LMV792 per channel	−40°C ≤ T_J ≤ 125°C			1.85
		Shutdown mode, V_EN < 0.4 per channel	T_J = 25 °C			0.02	1	μA
		Shutdown mode, V_EN < 0.4 per channel	−40°C ≤ T_J ≤ 125°C				5	μA
SR	Slew rate	A_V = +1, Rising (10% to 90%)				8.5		V/μs
SR	Slew rate	A_V = +1, Falling (90% to 10%)				10.5		V/μs
GBW	Gain bandwidth					14		MHz
e_n	Input referred voltage noise density	f = 1 kHz				6.2		nV/√Hz
i_n	Input referred current noise density	f = 1 kHz				0.01		pA/√Hz
t_on	Turnon time					140		ns
t_off	Turnoff time					1000		ns
V_EN	Enable pin voltage range	Enable mode			2.1	2		V
V_EN	Enable pin voltage range	Shutdown mode				0.5	0.4	V
I_EN	Enable pin input current	Enable mode V_EN = 2.5 V⁽⁴⁾				1.5	3	μA
I_EN	Enable pin input current	Shutdown mode V_EN = 0 V⁽⁴⁾				0.003	0.1	μA
THD+N	Total harmonic distortion + noise	f = 1 kHz, A_V = 1, R_LOAD = 600 Ω				0.01%

(1) Typical values represent the parametric norm at the time of characterization.

(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the statistical quality control (SQC) method.

(3) Offset voltage average drift is determined by dividing the change in V_OS by temperature change.

(4) Positive current corresponds to current flowing into the device.

(5) This parameter is specified by design and/or characterization and is not tested in production.

(6) The short circuit test is a momentary test, the short circuit duration is 1.5 ms.

6.6 5-V Electrical Characteristics

Unless otherwise specified, all limits are ensured for T_J = 25°C, V⁺ = 5 V, V⁻ = 0 V, V_CM = V⁺/2 = V_O, V_EN = V⁺.

PARAMETER		TEST CONDITIONS			MIN⁽²⁾	TYP⁽¹⁾	MAX⁽²⁾	UNIT
V_OS	Input offset voltage	T_J = 25 °C				0.1	±1.35	mV
V_OS	Input offset voltage	−40°C ≤ T_J ≤ 125°C					±1.65	mV
TC V_OS	Input offset voltage temperature drift	LMV791⁽³⁾				−1		μV/°C
TC V_OS	Input offset voltage temperature drift	LMV792⁽³⁾				−1.8		μV/°C
I_B	Input bias current	V_CM = 2 V⁽⁴⁾ ⁽⁵⁾	T_J = 25 °C			0.1	1	pA
			−40°C ≤ T_J ≤ 85°C				25
			−40°C ≤ T_J ≤ 125°C				100
I_OS	Input offset current	V_CM = 2 V⁽⁵⁾				10		fA
CMRR	Common-mode rejection ratio	0 V ≤ V_CM ≤ 3.7 V	T_J = 25 °C		80	100		dB
CMRR	Common-mode rejection ratio	0 V ≤ V_CM ≤ 3.7 V	−40°C ≤ T_J ≤ 125°C		75			dB
PSRR	Power supply rejection ratio	2.0V ≤ V⁺ ≤ 5.5 V, V_CM = 0 V	T_J = 25 °C		80	100		dB
		2.0V ≤ V⁺ ≤ 5.5 V, V_CM = 0 V	−40°C ≤ T_J ≤ 125°C		75
		1.8V ≤ V⁺ ≤ 5.5 V, V_CM = 0 V			80	98
CMVR	Common-mode voltage range	CMRR ≥ 60 dB	T_J = 25 °C		−0.3		4	V
CMVR	Common-mode voltage range	CMRR ≥ 55 dB	−40°C ≤ T_J ≤ 125°C		−0.3		4	V
A_VOL	Open-loop voltage gain	V_OUT = 0.3V to 4.7V, R_LOAD = 2 kΩ to V⁺/2	LMV791	T_J = 25 °C	85	97		dB
			LMV791	−40°C ≤ T_J ≤ 125°C	80
			LMV792	T_J = 25 °C	82	89
			LMV792	−40°C ≤ T_J ≤ 125°C	78
		V_OUT = 0.3V to 4.7V, R_LOAD = 10 kΩ to V⁺/2	T_J = 25 °C		88	110
		V_OUT = 0.3V to 4.7V, R_LOAD = 10 kΩ to V⁺/2	−40°C ≤ T_J ≤ 125°C		84
V_OUT	Output voltage swing high	R_LOAD = 2 kΩ to V⁺/2	T_J = 25 °C			35	75	mV from either rail
		R_LOAD = 2 kΩ to V⁺/2	−40°C ≤ T_J ≤ 125°C				82
		R_LOAD = 10 kΩ to V⁺/2	T_J = 25 °C			25	65
		R_LOAD = 10 kΩ to V⁺/2	−40°C ≤ T_J ≤ 125°C				71
	Output voltage swing low	R_LOAD = 2 kΩ to V⁺/2	LMV791	T_J = 25 °C		42	75
			LMV791	−40°C ≤ T_J ≤ 125°C			78
			LMV792	T_J = 25 °C		45	80
			LMV792	−40°C ≤ T_J ≤ 125°C			83
		R_LOAD = 10 kΩ to V⁺/2	T_J = 25 °C			20	65
		R_LOAD = 10 kΩ to V⁺/2	−40°C ≤ T_J ≤ 125°C				67
I_OUT	Output current	Sourcing to V⁻ V_IN = 200 mV⁽⁶⁾	T_J = 25 °C		45	60		mA
		Sourcing to V⁻ V_IN = 200 mV⁽⁶⁾	−40°C ≤ T_J ≤ 125°C		37
		Sinking to V⁺ V_IN = –200 mV⁽⁶⁾	T_J = 25 °C		10	21
		Sinking to V⁺ V_IN = –200 mV⁽⁶⁾	−40°C ≤ T_J ≤ 125°C		6
I_S	Supply current per amplifier	Enable mode V_EN ≥ 4.6 V	LMV791	T_J = 25 °C		1.15	1.4	mA
			LMV791	−40°C ≤ T_J ≤ 125°C			1.75
			LMV792 per channel	T_J = 25 °C		1.3	1.7
			LMV792 per channel	−40°C ≤ T_J ≤ 125°C			2.05
		Shutdown mode (V_EN ≤ 0.4 V)	T_J = 25 °C			0.14	1	μA
		Shutdown mode (V_EN ≤ 0.4 V)	−40°C ≤ T_J ≤ 125°C				5	μA
SR	Slew rate	A_V = +1, Rising (10% to 90%)			6	9.5		V/μs
SR	Slew rate	A_V = +1, Falling (90% to 10%)			7.5	11.5		V/μs
GBW	Gain bandwidth					17		MHz
e_n	Input referred voltage noise density	f = 1 kHz				5.8		nV/√Hz
i_n	Input referred current noise density	f = 1 kHz				0.01		pA/√Hz
t_on	Turnon time					110		ns
t_off	Turnoff time					800		ns
V_EN	Enable pin voltage range	Enable mode			4.6	4.5		V
V_EN	Enable pin voltage range	Shutdown mode				0.5	0.4	V
I_EN	Enable pin input current	Enable mode V_EN = 5 V⁽⁴⁾				5.6	10	μA
I_EN	Enable pin input current	Shutdown mode V_EN = 0 V⁽⁴⁾				0.005	0.2	μA
THD+N	Total harmonic distortion + noise	f = 1 kHz, A_V = 1, R_LOAD = 600 Ω				0.01%

(1) Typical values represent the parametric norm at the time of characterization.

(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the statistical quality control (SQC) method.

(3) Offset voltage average drift is determined by dividing the change in V_OS by temperature change.

(4) Positive current corresponds to current flowing into the device.

(5) This parameter is specified by design and/or characterization and is not tested in production.

(6) The short circuit test is a momentary test, the short circuit duration is 1.5 ms.

(7) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

6.7 Typical Characteristics

Unless otherwise specified, T_A = 25°C, V^– = 0, V⁺ = Supply Voltage = 5V, V_CM = V⁺/2, V_EN = V⁺.

Figure 1. Supply Current vs Supply Voltage (LMV791)

Figure 3. Supply Current vs
Supply Voltage in Shutdown Mode

Figure 5. V_OS vs V_CM

Figure 7. V_OS vs Supply Voltage

Figure 9. Supply Current vs Enable Pin Voltage (LMV791)

Figure 11. Supply Current vs Enable Pin Voltage (LMV792)

Figure 13. Input Bias Current vs V_CM

Figure 15. Sourcing Current vs Supply Voltage

Figure 17. Sourcing Current vs Output Voltage

Figure 19. Positive Output Swing vs Supply Voltage

Figure 21. Positive Output Swing vs Supply Voltage

Figure 23. Positive Output Swing vs Supply Voltage

Figure 25. Input Referred Voltage Noise vs Frequency

Figure 27. Overshoot and Undershoot vs C_LOAD

Figure 29. THD+N vs Peak-to-Peak Output Voltage (V_OUT)

Figure 31. THD+N vs Frequency

Figure 33. Open-Loop Gain and Phase With Resistive Load

Figure 35. Crosstalk Rejection

A_V = +1

Figure 37. Large Signal Transient Response

A_V = +1

Figure 39. Large Signal Transient Response

Figure 41. Phase Margin vs Capacitive Load (Stability)

Figure 43. Negative PSRR vs Frequency

Figure 45. Input Common-Mode Capacitance vs V_CM

Figure 2. Supply Current vs Supply Voltage (LMV792)

Figure 4. V_OS vs V_CM

Figure 6. V_OS vs V_CM

Figure 8. Slew Rate vs Supply Voltage

Figure 10. Supply Current vs Enable Pin Voltage(LMV791)

Figure 12. Supply Current vs Enable Pin Voltage (LMV792)

Figure 14. Input Bias Current vs V_CM

Figure 16. Sinking Current vs Supply Voltage

Figure 18. Sinking Current vs Output Voltage

Figure 20. Negative Output Swing vs Supply Voltage

Figure 22. Negative Output Swing vs Supply Voltage

Figure 24. Negative Output Swing vs Supply Voltage

Figure 26. Time Domain Voltage Noise

Figure 28. THD+N vs Peak-to-Peak Output Voltage (V_OUT)

Figure 30. THD+N vs Frequency

Figure 32. Open-Loop Gain and Phase With Capacitive Load

Figure 34. Closed-Loop Output Impedance vs Frequency

A_V = +1

Figure 36. Small Signal Transient Response

A_V = +1

Figure 38. Small Signal Transient Response

Figure 40. Phase Margin vs Capacitive Load (Stability)

Figure 42. Positive PSRR vs Frequency

Figure 44. CMRR vs Frequency