SNAS883A June   2024  – May 2025 LMX1860-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier
          1. 6.3.3.4.1 General Information about the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Lock Detect for the Clock Multiplier
          5. 6.3.3.4.5 Watchdog Timer
      4. 6.3.4 LOGICLK Output
        1. 6.3.4.1 LOGICLK Output Format
        2. 6.3.4.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      5. 6.3.5 SYSREF
        1. 6.3.5.1 SYSREF Output Buffers
          1. 6.3.5.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.5.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.5.2 SYSREF Frequency and Delay Generation
        3. 6.3.5.3 SYSREFREQ Pins and SYSREFREQ_FORCE Field
          1. 6.3.5.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.5.3.2 SYSREFREQ Windowing Feature
            1. 6.3.5.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.5.3.2.2 SYSREFREQ Repeater Mode With Delay Generation (Retime)
            3. 6.3.5.3.2.3 Other Guidance For SYSREF Windowing
            4. 6.3.5.3.2.4 For Glitch-Free Output
            5. 6.3.5.3.2.5 If Using SYNC Feature
          3. 6.3.5.3.3 SYNC Feature
    4. 6.4 Device Functional Modes Configurations
      1. 6.4.1 Pin Mode Control
        1. 6.4.1.1 Chip Enable (CE)
        2. 6.4.1.2 Output Channel Control
        3. 6.4.1.3 Logic Output Control
        4. 6.4.1.4 SYSREF Output Control
        5. 6.4.1.5 Device Mode Selection
        6. 6.4.1.6 Divider or Multiplier Value Selection
        7. 6.4.1.7 Calibration Control Pin
        8. 6.4.1.8 Output Power Control
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 SYSREFREQ Input Configuration
      2. 7.1.2 Treatment of Unused Pins
      3. 7.1.3 Current Consumption
    2. 7.2 Typical Applications
      1. 7.2.1 Local Oscillator Distribution Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Plot
      2. 7.2.2 JESD204B/C Clock Distribution Application
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power-Up Timing
    5. 7.5 Register Map
      1. 7.5.1 Device Registers
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PAP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.3.3 Clock Divider

Set the CLK_MUX to Divided to a divide value by 2, 3, 4, 5, and 7. This is set by the CLK_DIV word. When using the clock divider, any change to the input frequency requires the CLK_DIV_RST bit to be toggled from 1 to 0.

Table 6-4 Clock Divider
CLK_DIV DIVIDE DUTY CYCLE
0 Reserved N/A
1 2 50%
2 3 33%
3 4 50%
4 5 40%
5 Reserved N/A
6 7 43%
7 Reserved N/A