SNAS883A June   2024  – May 2025 LMX1860-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier
          1. 6.3.3.4.1 General Information about the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Lock Detect for the Clock Multiplier
          5. 6.3.3.4.5 Watchdog Timer
      4. 6.3.4 LOGICLK Output
        1. 6.3.4.1 LOGICLK Output Format
        2. 6.3.4.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      5. 6.3.5 SYSREF
        1. 6.3.5.1 SYSREF Output Buffers
          1. 6.3.5.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.5.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.5.2 SYSREF Frequency and Delay Generation
        3. 6.3.5.3 SYSREFREQ Pins and SYSREFREQ_FORCE Field
          1. 6.3.5.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.5.3.2 SYSREFREQ Windowing Feature
            1. 6.3.5.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.5.3.2.2 SYSREFREQ Repeater Mode With Delay Generation (Retime)
            3. 6.3.5.3.2.3 Other Guidance For SYSREF Windowing
            4. 6.3.5.3.2.4 For Glitch-Free Output
            5. 6.3.5.3.2.5 If Using SYNC Feature
          3. 6.3.5.3.3 SYNC Feature
    4. 6.4 Device Functional Modes Configurations
      1. 6.4.1 Pin Mode Control
        1. 6.4.1.1 Chip Enable (CE)
        2. 6.4.1.2 Output Channel Control
        3. 6.4.1.3 Logic Output Control
        4. 6.4.1.4 SYSREF Output Control
        5. 6.4.1.5 Device Mode Selection
        6. 6.4.1.6 Divider or Multiplier Value Selection
        7. 6.4.1.7 Calibration Control Pin
        8. 6.4.1.8 Output Power Control
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 SYSREFREQ Input Configuration
      2. 7.1.2 Treatment of Unused Pins
      3. 7.1.3 Current Consumption
    2. 7.2 Typical Applications
      1. 7.2.1 Local Oscillator Distribution Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Plot
      2. 7.2.2 JESD204B/C Clock Distribution Application
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power-Up Timing
    5. 7.5 Register Map
      1. 7.5.1 Device Registers
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PAP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

2.4V ≤ VCC ≤ 2.6V, –55°C ≤ TC ≤ +125°C. Typical values are at VCC = 2.5V, 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Consumption
ICC Supply Current (1) Powered up, all outputs and SYSREF on 1050 mA
Powered up, all outputs on, all SYSREF off 600
Powered up, all outputs and SYSREF off 265
Powered down(2) 11
SYSREF
fSYSREF SYSREF output frequency Generator mode 200 MHz
Repeater mode 100 MHz
Δt SYSREF delay step size fCLKIN = 12.8GHz 3 ps
tRISE Rise time (20% to 80%) SYSREFOUT 45 ps
LOGISYSREFOUT CML 120 ps
LVDS 120 ps
tFALL Fall time (20% to 80%) SYSREFOUT 45 ps
LOGISYSREFOUT CML 120 ps
LVDS 120 ps
VOD Differential output voltage SYSREFOUT 0.85 Vpp
LOGISYSREFOUT CML 0.4 Vp
LVDS 0.4 Vp
VSYSREFCM Common mode voltage SYSREFOUT CML
SYSREFOUTx_PWR=4
100Ω Differential Load		 0.8 V
SYSREFREQ Pins
VSYSREFIN Voltage input range AC differential voltage 0.8 2 Vpp
VCM Input common mode Differential 100Ω Termination, DC coupled
Set externally		 1.2 1.3 2 V
Clock Input
fIN Input frequency Buffer Mode Only 0.3 15(3) GHz
PIN Input power Single-ended power at CLKIN_P or CLKIN_N 0 10 dBm
Clock Outputs
fOUT Output frequency Divide-by-2 0.15 6.4 GHz
fOUT Output frequency Buffer Mode 0.3 15(3)
fOUT Output frequency x2, x3, x4 3.2 6.4
fOUT Output frequency LOGICLK output 1 800 MHz
tCAL Calibration-time Multiplier calibration time fIN = 3.2GHz; x2
fSMCLK = 28MHz		 750 µs
pOUT Output power Single-Ended fCLKLOUT = 6GHz
OUTx_PWR = 7		 6 dBm
fCLKLOUT = 12.8GHz
OUTx_PWR = 7		 0
fCLKLOUT = 15GHz
OUTx_PWR = 7		 -3
tRISE Rise time (20% to 80%) fCLKOUT = 300MHz 45 ps
tFALL Fall time (20% to 80%) fCLKOUT = 300MHz 45 ps
tMUTE Output mute time Falling edge of OE pin 30 µs
tUNMUTE Output unmute time Rising edge of OE pin 30 µs
Propagation Delay and Skew
| tSKEW | Magnitude of skew between outputs TA = -55°C to +125°C 2.5 10 ps
ΔtDLY/ΔT Propagation delay variation over temp Buffer Mode 0.02 0.06 0.1 ps/C
tDLY Propagation delay Buffer Mode TA = 25°C 180 ps
Divider Mode 182
Multiplier Mode 185
Noise, Jitter, and Spurs
JCKx Additive jitter Additive Jitter. 12kHz to 100MHz integration bandwidth. Buffer Mode 5 fs, rms
x2 Multiplier 16
x3 Multiplier 21
x4 Multiplier 26
Flicker 1/f flicker noise Slew Rate > 8V/ns, fCLK=6GHz Buffer Mode –155 dBc/Hz
NFL Noise Floor fOUT = 6GHz; fOffset = 100MHz Buffer Mode –159 dBc/Hz
Divide-by-2 –158.5
Multiplier (x2,x3,x4) –159.5
Noise Floor LOGICLK output, 300MHz CML –150.5 dBc/Hz
LVDS –151.5
H2 Second harmonic fOUT = 6GHz (differential), Buffer Mode –25 dBc
fOUT = 6GHz (single-ended), Buffer Mode –13
fOUT = 6GHz, single-ended, Divide by 2 –16
H1/2 Input clock leakage spur fOUT = 6GHz (single-ended) x2 (fSPUR = 3GHz) –40 dBc
H1/3 x3 (fSPUR = 2GHz) –50
H1/4 x4 (fSPUR = 1.5GHz) –54 dBc
ISPUR LOGICLK to CLKOUT fSPUR = 300MHz (differential) –70 dBc
Digital Interface (SCK, SDI, CS#, MUXOUT,CLKx_EN,MUXSELx,PWRSELx,DIVSELx,LOGIC_EN,SYSREF_EN,CAL,CE)
VIH High-level input voltage SCK, SDI, CS# 1.4 3.3 V
High-level input voltage CLKx_EN,MUXSELx,PWRSELx,DIVSELx,LOGIC_EN,SYSREF_EN,CAL,CE 1.4 3.3 V
VIL Low-level input voltage SCK, SDI, CS# 0 0.4 V
Low-level input voltage CLKx_EN,MUXSELx,PWRSELx,DIVSELx,LOGIC_EN,SYSREF_EN,CAL,CE 0 0.4 V
IIH High-level input current SCK, SDI, CS# –42 42 µA
High-level input current CLKx_EN,MUXSELx,PWRSELx,DIVSELx,LOGIC_EN,SYSREF_EN,CAL,CE –42 42 µA
IIL Low-level input current SCK, SDI, CS# –25 25 µA
Low-level input current CLKx_EN,MUXSELx,PWRSELx,DIVSELx,LOGIC_EN,SYSREF_EN,CAL,CE –25 25 µA
VOH High-level output voltage MUXOUT IOH = 5mA 1.4 2.2 V
High-level output voltage IOH = 0.1mA 2.2 2.5 V
VOL Low-level output voltage MUXOUT IOL = 5mA 0.45 V
(1) Unless Otherwise Stated, fCLKIN=6GHz, CLK_MUX=Buffer, All clocks on with OUTx_PWR=7, SYSREFREQ_MODE=1.
(2) For powered down mode.
(3) SYNC, divider, SYSREF and SYSREF windowing supported up to 12.8GHz frequency.