8.2.2.1 Enable Divider, R_ENT, R_ENB and R_ENH Selection

Internal to the module is a 2-MΩ pullup resistor connected from V_IN to Enable. For applications not requiring precision undervoltage lockout (UVLO), the Enable input may be left open circuit and the internal resistor will always enable the module. In such case, the internal UVLO occurs typically at 4.3V (V_IN rising).

In applications with separate supervisory circuits Enable can be directly interfaced to a logic source. In the case of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the LMZ12008 output rail.

Enable provides a precise 1.274-V threshold to allow direct logic drive or connection to a voltage divider from a higher enable voltage such as V_IN. Additionally there is 13 μA (typical) of switched offset current allowing programmable hysteresis. See Figure 48.

The function of the enable divider is to allow the designer to choose an input voltage below which the circuit will be disabled. This implements the feature of a programmable UVLO. The two resistors must be chosen based on the following ratio:

The LMZ12008 typical application shows 12.7 kΩ for R_ENB and 42.2 kΩ for R_ENT resulting in a rising UVLO of 5.51 V. This divider presents 4.62 V to the EN input when V_IN is raised to 20 V. This upper voltage must always be checked, making sure that it never exceeds the Abs Max 5.5-V limit for Enable. A 5.1-V Zener clamp can be applied in cases where the upper voltage would exceed the EN input's range of operation. The Zener clamp is not required if the target application prohibits the maximum Enable input voltage from being exceeded.

Additional enable voltage hysteresis can be added with the inclusion of R_ENH. It is possible to select values for R_ENT and R_ENB such that R_ENH is a value of zero allowing it to be omitted from the design.

Rising threshold can be calculated as follows:

Whereas the falling threshold level can be calculated using:

Figure 48. Enable Input Detail

8.2.2.2 Output Voltage Selection

Output voltage is determined by a divider of two resistors connected between V_OUT and AGND. The midpoint of the divider is connected to the FB input.

The regulated output voltage determined by the external divider resistors R_FBT and R_FBB is:

Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:

These resistors must generally be chosen from values in the range of 1.0 kΩ to 10.0 kΩ.

For V_OUT = 0.8 V the FB pin can be connected to the output directly and R_FBB can be set to 8.06 kΩ to provide minimum output load.

Table 1 lists the values for R_FBT , and R_FBB.

8.2.2.3 Soft-Start Capacitor Selection

Programmable soft-start permits the regulator to slowly ramp to its steady-state operating point after being enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time.

Upon turnon, after all UVLO conditions have been passed, an internal 1.6-ms circuit slowly ramps the SS input to implement internal soft start. If 1.6 ms is an adequate turnon time then the Css capacitor can be left unpopulated. Longer soft-start periods are achieved by adding an external capacitor to this input.

Soft-start duration is given by the formula:

This equation can be rearranged as follows:

Using a 0.22-μF capacitor results in 3.5-ms typical soft-start duration; and 0.47-μF results in 7.5 ms typical. 0.47 μF is a recommended initial value.

As the soft-start input exceeds 0.795 V the output of the power stage will be in regulation and the 50-μA current is deactivated. The following conditions will reset the soft-start capacitor by discharging the SS input to ground with an internal current sink.

• The Enable input being pulled low
• A thermal shutdown condition
• V_IN falling below 4.3 V (typical) and triggering the V_CC UVLO

8.2.2.4 Tracking Supply Divider Option

The tracking function allows the module to be connected as a slave supply to a primary voltage rail (often the 3.3-V system rail) where the slave module output voltage is lower than that of the master. Proper configuration allows the slave rail to power up coincident with the master rail such that the voltage difference between the rails during ramp-up is small (that is, < 0.15 V typical). The values for the tracking resistive divider must be selected such that the effect of the internal 50-µA current source is minimized. In most cases the ratio of the tracking divider resistors is the same as the ratio of the output voltage setting divider. Proper operation in tracking mode dictates the soft-start time of the slave rail be shorter than the master rail; a condition that is easy to satisfy since the C_SS cap is replaced by R_TKB. The tracking function is only supported for the power up interval of the master supply; once the SS/TRK rises past 0.795 V the input is no longer enabled and the 50-µA internal current source is switched off.

Figure 49. Tracking Option Input Detail

8.2.2.5 C_OUT Selection

None of the required C_OUT output capacitance is contained within the module. A minimum value ranging from 330 μF for 6-V_OUT to 660 μF for 1.2-V_OUT applications is required based on the values of internal compensation in the error amplifier. These minimum values can be decreased if the effective capacitor ESR is higher than 15 mΩ.

A Low ESR (15 mΩ) tantalum, organic semiconductor or specialty polymer capacitor types in parallel with a 47-nF X7R ceramic capacitor for high-frequency noise reduction is recommended for obtaining lowest ripple. The output capacitor C_OUT may consist of several capacitors in parallel placed in close proximity to the module. The output voltage ripple of the module depends on the equivalent series resistance (ESR) of the capacitor bank, and can be calculated by multiplying the ripple current of the module by the effective impedance of your chosen output capacitors (for ripple current calculation, see Equation 2. Electrolytic capacitors will have large ESR and lead to larger output ripple than ceramic or polymer types. For this reason a combination of ceramic and polymer capacitors is recommended for low output ripple performance.

The output capacitor assembly must also meet the worst case ripple current rating of Δi_L, as calculated in Equation 2 below. Loop response verification is also valuable to confirm closed loop behavior.

For applications with dynamic load steps; Equation 10 provides a good first pass approximation of C_OUT for load transient requirements.

Equation 10.

For 12 V_IN, 3.3 V_OUT, a transient voltage of 5% of V_OUT = 0.165 V (ΔV_OUT), a 7A load step (I_STEP), an output capacitor effective ESR of 3 mΩ, and a switching frequency of 350 kHz (f_SW):

Equation 11.

One recommended output capacitor combination is two 330-μF, 15-mΩ ESR tantalum polymer capacitors connected in parallel with a 47-µF 6.3-V X5R ceramic. This combination provides excellent performance that may exceed the requirements of certain applications. Additionally some small 47-nF ceramic capacitors can be used for high frequency EMI suppression.

8.2.2.6 C_IN Selection

The LMZ12008 module contains two internal ceramic input capacitors. Additional input capacitance is required external to the module to handle the input ripple current of the application. The input capacitor can be several capacitors in parallel. This input capacitance must be located in very close proximity to the module. Input capacitor selection is generally directed to satisfy the input ripple current requirements rather than by capacitance value. Input ripple current rating is dictated by Equation 12:

Equation 12.

where

• D ≊ V_OUT / V_IN

As a point of reference, the worst case ripple current will occur when the module is presented with full load current and when V_IN = 2 × V_OUT.

Recommended minimum input capacitance is 30-µF X7R (or X5R) ceramic with a voltage rating at least 25% higher than the maximum applied input voltage for the application. TI also recommends to pay attention to the voltage and temperature derating of the capacitor selected.

If the system design requires a certain minimum value of peak-to-peak input ripple voltage (ΔV_IN) to be maintained then Equation 13 may be used.

Equation 13.

If ΔV_IN is 200 mV or 1.66% of V_IN for a 12-V input to 3.3-V output application and f_SW = 350 kHz then:

Equation 14.

Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input capacitance and parasitic inductance of the incoming supply lines. The LMZ12008 typical applications schematic and evaluation board include a 150-μF 50-V aluminum capacitor for this function. There are many situations where this capacitor is not necessary.