10.1 Layout Guidelines

PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. A good layout example is shown in Figure 55

1. Minimize area of switched current loops.

From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PCB layout as shown in Figure 53. The high current loops that do not overlap have high di/dt content that will cause observable high frequency noise on the output pin if the input capacitor (C_IN) is placed at a distance away from the LMZ12008. Therefore place C_IN as close as possible to the LMZ12008 VIN and PGND exposed pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output capacitor must consist of a localized top side plane that connects to the PGND exposed pad (EP).

2. Have a single point ground.

The ground connections for the feedback, soft-start, and enable components must be routed to the AGND pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Additionally provide a single point ground connection from pin 4 (AGND) to EP/PGND.

3. Minimize trace length to the FB pin.

Both feedback resistors, R_FBT and R_FBB must be located close to the FB pin. Since the FB node is high impedance, maintain the copper area as small as possible. The traces from R_FBT, R_FBB must be routed away from the body of the LMZ12008 to minimize possible noise pickup.

4. Make input and output bus connections as wide as possible.

This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so will correct for voltage drops and provide optimum output accuracy.

5. Provide adequate device heat-sinking.

Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be connected to inner layer heat-spreading ground planes. For best results use a 10 × 10 via array or larger with a minimum via diameter of 8 mil thermal vias spaced 46.8 mil (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction temperature below 125°C.

10.2 Layout Examples

Figure 53. Critical Current Loops to Minimize

Figure 54. PCB Layout Guide

Figure 55. Top View of Evaluation PCB

Figure 56. Bottom View of Evaluation PCB

10.3 Power Dissipation and Thermal Considerations

When calculating module dissipation use the maximum input voltage and the average output current for the application. Many common operating conditions are provided in the characteristic curves such that less common applications can be derived through interpolation. In all designs, the junction temperature must be kept below the rated maximum of 125°C.

For the design case of V_IN = 12 V, V_OUT = 3.3 V, I_OUT = 8 A, and T_A-MAX = 50°C, the module must see a thermal resistance from case to ambient (θ_CA) of less than:

Equation 15.

Given the typical thermal resistance from junction to case (θ_JC) to be 1.0°C/W. Use the 85°C power dissipation curves in the Typical Characteristics section to estimate the P_IC-LOSS for the application being designed. In this application it is 3.9 W.

Equation 16.

To reach θ_CA = 18.23, the PCB is required to dissipate heat effectively. With no airflow and no external heat-sink, a good estimate of the required board area covered by 2-oz. copper on both the top and bottom metal layers is:

Equation 17.

As a result, approximately 27.42 square cm of 2-oz. copper on top and bottom layers is the minimum required area for the example PCB design. This is 5.23 × 5.23 cm (2.06 × 2.06 in) square. The PCB copper heat sink must be connected to the exposed pad. For best performance, use approximately 100, 8 mil thermal vias spaced 59 mil (1.5 mm) apart connect the top copper to the bottom copper.

Another way to estimate the temperature rise of a design is using θ_JA. An estimate of θ_JA for varying heat sinking copper areas and airflows can be found in the typical applications curves. If our design required the same operating conditions as before but had 225 LFPM of airflow. We locate the required θ_JA of

Equation 18.

On the θ_RA vs copper heatsinking curve, the copper area required for this application is now only 1 square inches. The airflow reduced the required heat sinking area by a factor of four.

To reduce the heat sinking copper area further, this package is compatable with D3-PAK surface mount heat sinks.

For an example of a high thermal performance PCB layout for SIMPLE SWITCHER power modules, refer to AN-2093 SNVA460, AN-2084 SNVA456, AN-2125 SNVA473, AN-2020 SNVA422 and AN-2026 SNVA424.

10.4 Power Module SMT Guidelines

The recommendations below are for a standard module surface mount assembly

• Land Pattern — Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads
• Stencil Aperture
  • For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land pattern
  • For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
• Solder Paste — Use a standard SAC Alloy such as SAC 305, type 3 or higher
• Stencil Thickness — 0.125 to 0.15 mm
• Reflow — Refer to solder paste supplier recommendation and optimized per board size and density
• Refer to Design Summary LMZ1xxx and LMZ2xxx Power Modules Family (SNAA214) for reflow information
• Maximum number of reflows allowed is one

Figure 57. Sample Reflow Profile