SNOSCT6F March   2013  – January 2017 LP38798


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Noise Filter
      2. 7.3.2 Enable Input Operation
      3. 7.3.3 Undervoltage Lockout (UVLO)
      4. 7.3.4 Output Current Limiting
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Programming the Output Voltage
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: VOUT = 5 V
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Custom Design With WEBENCH® Tools
        2. Input Capacitor Recommendations
        3. Output Capacitor Recommendations
        4. Charge Pump
        5. Setting the Output Voltage
        6. Device Dissipation
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
    4. 10.4 Estimating the Junction Temperature
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Suppport
        1. Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description


The LP38798 is a positive voltage (20 V), ultra-low-noise (5 µVRMS), low-dropout (LDO) regulator capable of supplying a well-regulated, low-noise voltage to an 800-mA load. The LP38798 uses an advanced design with a CMOS process to deliver ultra low output noise and high PSRR at switching power supply (SMPS) frequencies.

Functional Block Diagram

LP38798 30204210.gif

Feature Description

Noise Filter

Any noise at LP38798 SET pin is reduced by an internal passive, first order low-pass RC filter before it is passed to the output buffer stage. The low-pass filter has a –3-dB cut-off frequency of approximately 0.08 Hz.

To keep the low-pass filter from interfering with the output voltage rise time at start-up, a voltage comparator keeps the filter in a fast-charge mode while the output voltage (VOUT) is less than 99.5% of the SET pin voltage (VSET) . When the rising VOUT is within 0.5% of VSET the fast-charge mode ends, and VOUT will rise the final 0.5% based on the RC time constant (τ = 2s) of the filter.

Should VOUT be more than 2% above the VSET voltage, a voltage comparator will put the filter into the fast-charge mode to allow the filter to discharge and VOUT to fall a value closer to VSET. When the falling VOUT is within 2% of VSET the fast-charge mode ends, and VOUT will fall the final 2% based on the RC time constant (τ = 2s) of the filter.

If the input voltage has an extended rise time, the output voltage may exhibit a stair-case waveform as the fast-charge mode is activated and de-activated as VSET rises with VIN, and VOUT follows. Once the VIN has risen above the programmed VSET voltage, and VOUT is within 0.5% of VSET, the stair-case behavior will end.

Enable Input Operation

The Enable pin (EN) is pulled high internally by a 2 μA (typical) current source from the IN pin, and internally clamped at 5 V (typical) by a zener. Pulling the EN pin low, by sinking the IEN current to ground, will turn the output off.

If the EN function is not needed the EN pin should be left open (floating). Do not connect the EN pin directly to VIN if there is any possibility that VIN might exceed 5.5 V (that is, EN pin AbsMax). If external pullup is required, the external current into the EN pin should be limited to no more than 10 μA.

Equation 1. RPULL-UP > (VPULL-UP – 5 V) / 10 μA )

Undervoltage Lockout (UVLO)

The LP38798 incorporates UVLO. The UVLO circuit monitors the input voltage and keeps the LP38798 disabled while a rising VIN is less than 2.65 V (typical). The rising UVLO threshold is approximately 350 mV below the recommended minimum operating VIN of 3 V.

Output Current Limiting

The LP38798 incorporates active output current limiting. The threshold for the output current limiting is set well above the ensured output operating current such that it does not interfere with normal operation.

Note that output current limiting is provided as a safety feature and is outside the recommended operating conditions. Operation at the current limit is not recommended as the device junction temperature (TJ) will rise rapidly and operation will likely cross into thermal shutdown behavior .

Thermal Shutdown

The LP38798 includes thermal protection that will shut-off the output current when activated by excessive device dissipation. Thermal shutdown (TSD) will occur when the junction temperature has risen to 170°C. The junction temperature must fall typically 12°C from the shutdown temperature for the output current to be restored. Junction temperature is calculated from the formula in Equation 2:

Equation 2. TJ = (TA + (PD × RθJA))

Where the power being dissipated, PD, is defined as:

Equation 3. PD = ((VIN – VOUT) × IOUT)


Thermal shutdown is provided as a safety feature and is outside the specified Operating Ratings temperature range. Operation with a junction temperature (TJ) above 125°C is not recommended as the device behavior is not specified.

Device Functional Modes

The LP38798 has two functional modes:

  1. Enabled: When the EN pin voltage is above the VEN(ON) threshold, and VIN is above the UVLO threshold, the device is enabled.
  2. Disabled: When the EN pin voltage is below the (VEN(ON) + ΔVEN) threshold, or VIN is below the UVLO threshold, the device is disabled.


Programming the Output Voltage

Current sourced from the SET pin, through R1 and R2, must be kept to less than 100 µA. The minimum allowed value for R2 is 12.9 kΩ.

Equation 4. ISET = VFB / R2
Equation 5. R2MIN = VFB(MAX) / 100 μA
Equation 6. R2MIN = 12.9 kΩ;

The values for R1 and R2 may be adjusted as needed to achieve the desired output voltage as long as the value for R2 is no less than 12.9 kΩ. The maximum recommended value for R2 is 100 kΩ.

Equation 7 is used to determine the output voltage:

Equation 7. VOUT = (VFB × (1 + (R1 / R2 ))) + VOS

Alternately, Equation 8 can be used to determine the appropriate R1 value for a given R2 value:

Equation 8. R1 = R2 × (((VOUT) / VFB) – 1) 

Table 1 suggests some ±1% values for R1 and R2 for a range of output voltages using the typical VFB value of 1.200V. This is not a definitive list, as other combinations exist that will provide similar, possibly better, performance.

Table 1. Typical R1 and R2 Values for Assorted Output Voltages

1.2 V 0 Ω 15 kΩ 1.2 V
1.5 V 4.22 kΩ 16.9 kΩ 1.5 V
1.8 V 10.5 kΩ 21 kΩ 1.8 V
2 V 10 kΩ 15 kΩ 2 V
2.5 V 16.2 kΩ 15.0 kΩ 2.496 V
3 V 21 kΩ 14 kΩ 3 V
3.3 V 23.2 kΩ 13.3 kΩ 3.293 V
5 V 47.5 kΩ 15 kΩ 5 V