SNOSCT6F March   2013  – January 2017 LP38798


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Noise Filter
      2. 7.3.2 Enable Input Operation
      3. 7.3.3 Undervoltage Lockout (UVLO)
      4. 7.3.4 Output Current Limiting
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Programming the Output Voltage
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: VOUT = 5 V
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Custom Design With WEBENCH® Tools
        2. Input Capacitor Recommendations
        3. Output Capacitor Recommendations
        4. Charge Pump
        5. Setting the Output Voltage
        6. Device Dissipation
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
    4. 10.4 Estimating the Junction Temperature
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Suppport
        1. Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Layout Guidelines

The dynamic performance of the LP38798 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP38798.

Best performance is achieved by placing all of the components on the same side of the PCB as the LP38798, and as close as is practical to the LP38798 package. All component ground connections must be back to the LP38798 analog ground connection using as wide and short of a copper trace as is practical. The connection from the FB pin to the VSET resistors must be as short as possible as the FB pin is a high impedance input. Any trace length on the FB pin acts as an antenna.

Connections using long trace lengths, narrow trace widths; avoid connections through vias, which add parasitic inductances and resistance that results in inferior performance especially during transient conditions.

A ground plane, either on the opposite side of a two-layer PCB, or embedded in a multi-layer PCB, is strongly recommended. This Ground Plane serves two purposes :

  1. Provides a circuit reference plane to assure accuracy, and
  2. Provides a thermal plane to remove heat from the LP38798 through thermal vias under the package DAP.

Layout Example

LP38798 LP38798_PCB_layout.gif

Thermal Considerations

The value of RθJA for the 12-lead WSON package is specifically dependent on PCB copper area, copper thickness, the number of layers, and thermal vias under the exposed thermal pad (DAP). Refer to A Guide to Board Layout for Best Thermal Resistance for Exposed Packages for general guidelines for mounting packages with exposed thermal pads.

Exceeding the maximum allowable power dissipation defined by the final RθJA will cause excessive die temperature, and the regulator may go into thermal shutdown.

Estimating the Junction Temperature

The EIA/JEDEC standard (JESD51-2) provides methodologies to estimate the junction temperature from external measurements (ΨJB references the temperature at the PCB, and ΨJT references the temperature at the top surface of the package) when operating under steady-state power dissipation conditions. These methodologies have been determined to be relatively independent of the copper thermal spreading area that may be attached to the package DAP when compared to the more typical RθJA. Refer to Semiconductor and IC Package Thermal Metrics, for specifics.